神仙姐姐 发表于 2010-6-26 00:48:43

这个verilog程序不能综合成为状态机？

本帖最后由 fpgaw 于 2010-11-18 16:21 编辑

module max120(
input clk,n_rst,
input data120,
input busy120,
input long,
input choose_han,
input long_nh,
output reg AD_WR,over,
outputaddress_out,
output reg dout_real,
output reg data_reg,
output han_addr,
output reg ad_data_i,
output regstate,next_state
);
parameter
S0=3'd0,S1=3'd1,S2=3'd2,S3=3'd3,S4=3'd4,S5=3'd5;
parameter all_ones=32'hffffffff;
assign han_addr=address;
reg clk_10M_en;
reg address;
reg addr_max;
assign address_out={address,address,address,address,address,address,address};
always @(posedge clk)
begin
clk_10M_en<=clk_10M_en+1'b1;
end
always @(posedge clk or negedge n_rst)
begin
if(!n_rst)
state<=S0;
else if(clk_10M_en)
state<=next_state;
else
state<=state;
end
always @(state,busy120,addr_max)
begin
next_state=state;
case(state)
S0:begin
   if(!busy120) next_state=S0;
   elsenext_state=S1;
   end
S1:begin
   if(busy120)next_state=S1;
   elsenext_state=S2;
   end
S2:next_state=S3;
S3:next_state=S4;
S4:begin
   if(addr_max)next_state=S0;
   elsenext_state=S5;
   end
S5:next_state=S5;
default:next_state=S0;
endcase
end
always @(posedge clk or negedge n_rst)
begin
if(!n_rst)
begin
address<=7'd0;
AD_WR<=1'b0;
dout_real<=32'd0;
ad_data_i<=all_ones;
over<=1'b1;
data_reg<=12'd0;
end
else if(clk_10M_en)
case(next_state)
S0: ;
S1: ;
S2:data_reg<=data120+12'h800;
S3:begin
   if(choose_han)
   dout_real<=long;
   else
   dout_real<=long_nh;
   AD_WR<=1'b1;
   ad_data_i<=32'd0;
   end
S4:begin
   if(address!=7'd127)
   begin
   address<=address+1'b1;
   AD_WR<=1'b0;
   addr_max<=1'b1;
   end
   else
   begin
   addr_max<=1'b0;
   AD_WR<=1'b0;
   address<=7'd0;
   end
   end
S5: over<=1'b0;
default: ;
endcase
else ;
end
endmodule
程序很简单，是一个控制max120采样的程序，采集128个点。麻烦哪位大哥解释一下，并给出能综合成状态机的程序。

粉妮 发表于 2010-6-26 02:25:30

output reg&nbsp;&nbsp;state,next_state&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;什么意思啊？<br>
<br>
always @(state,busy120,addr_max)&nbsp; &nbsp;&nbsp;&nbsp;什么意思？<br>
begin<br>
&nbsp; &nbsp; next_state=state;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;这句有什么用？<br>
&nbsp; &nbsp; case(state)<br>
<br>
[ 本帖最后由 chshk 于 2009-7-9 17:45 编辑 ]

沉醉夕阳下 发表于 2010-6-26 03:58:12

我现在知道了，state和next_state不能拉成output

粉妮 发表于 2010-6-26 04:56:34

哈哈，提供了一个很好的教训

粉妮 发表于 2010-6-26 06:28:10

always @(state,busy120,addr_max)&nbsp; &nbsp;&nbsp;&nbsp;什么意思？<br>
begin<br>
&nbsp; &nbsp; next_state=state;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;这句有什么用？<br>
&nbsp; &nbsp; case(state)<br>
应该改为<br>
state=next_state;这样才对吧。

夜带水果刀 发表于 2010-6-26 08:16:57

ls的需要好好看书<br>
这段是组合逻辑算下一个状态<br>
哎

笨笨猪 发表于 2010-6-26 08:40:02

建议：写程序是注意一下格式和注释.

Sunlife 发表于 2015-4-7 11:07:01

    写程序注意一下格式和注释
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