这个verilog程序不能综合成为状态机？

module max120(
input clk,n_rst,
input [11:0]data120,
input busy120,
input [31:0]long,
input choose_han,
input [31:0]long_nh,
output reg AD_WR,over,
output[6:0]address_out,
output reg [31:0]dout_real,
output reg [11:0]data_reg,
output [6:0]han_addr,
output reg [31:0]ad_data_i,
output reg[2:0]state,next_state
  );
parameter
S0=3'd0,S1=3'd1,S2=3'd2,S3=3'd3,S4=3'd4,S5=3'd5;
parameter all_ones=32'hffffffff;
assign han_addr=address[6:0];
reg clk_10M_en;
reg [6:0]address;
reg addr_max;
assign address_out={address[0],address[1],address[2],address[3],address[4],address[5],address[6]};
always @(posedge clk)
begin
clk_10M_en<=clk_10M_en+1'b1;
end
always @(posedge clk or negedge n_rst)
begin
if(!n_rst)
state<=S0;
else if(clk_10M_en)
state<=next_state;
else
state<=state;
end
always @(state,busy120,addr_max)
begin
  next_state=state;
  case(state)
  S0:begin
   if(!busy120) next_state=S0;
   else  next_state=S1;
   end
  S1:begin
   if(busy120)  next_state=S1;
   else  next_state=S2;
   end
  S2:next_state=S3;
  S3:next_state=S4;
  S4:begin
   if(addr_max)next_state=S0;
   else  next_state=S5;
   end
  S5:next_state=S5;
  default:next_state=S0;
  endcase
end
always @(posedge clk or negedge n_rst)
begin
if(!n_rst)
begin
  address<=7'd0;
  AD_WR<=1'b0;
  dout_real<=32'd0;
  ad_data_i<=all_ones;
  over<=1'b1;
  data_reg<=12'd0;
end
else if(clk_10M_en)
  case(next_state)
  S0: ;
  S1: ;
  S2:data_reg<=data120+12'h800;
  S3:begin
   if(choose_han)
     dout_real<=long;
   else
     dout_real<=long_nh;
   AD_WR<=1'b1;
   ad_data_i<=32'd0;
   end
  S4:begin
   if(address!=7'd127)
   begin
     address<=address+1'b1;
     AD_WR<=1'b0;
     addr_max<=1'b1;
   end
   else
   begin
     addr_max<=1'b0;
     AD_WR<=1'b0;
     address<=7'd0;
   end
   end
  S5: over<=1'b0;
  default: ;
  endcase
else ;
end
endmodule
程序很简单，是一个控制max120采样的程序，采集128个点。麻烦哪位大哥解释一下，并给出能综合成状态机的程序。

output reg&nbsp;&nbsp;[2:0]state,next_state&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;什么意思啊？<br>
<br>
always @(state,busy120,addr_max)&nbsp; &nbsp;&nbsp;&nbsp;什么意思？<br>
begin<br>
&nbsp; &nbsp; next_state=state;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;这句有什么用？<br>
&nbsp; &nbsp; case(state)<br>
<br>
[ 本帖最后由 chshk 于 2009-7-9 17:45 编辑 ]

我现在知道了，state和next_state不能拉成output

哈哈，提供了一个很好的教训

always @(state,busy120,addr_max)&nbsp; &nbsp;&nbsp;&nbsp;什么意思？<br>
begin<br>
&nbsp; &nbsp; next_state=state;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;这句有什么用？<br>
&nbsp; &nbsp; case(state)<br>
应该改为<br>
state=next_state;这样才对吧。

ls的需要好好看书<br>
这段是组合逻辑算下一个状态<br>
哎

建议：写程序是注意一下格式和注释.

    写程序注意一下格式和注释