论坛 › FPGA技术交流 › VHDL状态机的时钟产生问题

VVC 发表于 2010-6-26 10:54:15

可以采用并行输出寄存器的译码输出，缩短输出到管脚的延时，见下贴<br>
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[ 本帖最后由 rose8866 于 2007-6-25 20:40 编辑 ]

CTT 发表于 2010-6-26 12:23:06

library ieee ; <br>
use ieee.std_logic_1164.all ;<br>
entity cycles is <br>
port (<br>
&nbsp; &nbsp;&nbsp; &nbsp;clock_main , rst: in std_logic ;<br>
&nbsp; &nbsp;&nbsp; &nbsp;c0, c1, c2, c3 : out std_logic) ;<br>
end cycles ;<br>
architecture rtl of cycles is<br>
type state_values is (st0 , st1 , st2 ,&nbsp;&nbsp;st3) ;<br>
signal pres_state , next_state : state_values ;<br>
signal tmpc0,tmpc1,tmpc2,tmpc3 : std_logic;<br>
begin<br>
process(pres_state)<br>
begin<br>
case pres_state is<br>
&nbsp;&nbsp;when st0 =&gt;<br>
&nbsp; &nbsp;next_state &lt;= st1 ;<br>
&nbsp;&nbsp;when st1 =&gt;<br>
&nbsp; &nbsp; next_state &lt;= st2 ;<br>
&nbsp;&nbsp;when st2 =&gt;<br>
&nbsp; &nbsp;next_state &lt;= st3 ;<br>
&nbsp;&nbsp;when st3 =&gt;<br>
&nbsp; &nbsp;next_state &lt;= st0 ;<br>
&nbsp;&nbsp;when others =&gt;<br>
&nbsp; &nbsp;next_state &lt;= st0 ;<br>
end case ;<br>
end process;<br>
with next_state select&nbsp; &nbsp;&nbsp;&nbsp;--根据次态预先将c0,c0,c1,c2数据放到输出寄存器<br>
&nbsp; &nbsp; tmpc0 &lt;= '1' when st0,<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; '0' when others;<br>
with next_state select<br>
&nbsp; &nbsp; tmpc1 &lt;= '1' when st1,<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; '0' when others;<br>
with next_state select<br>
&nbsp; &nbsp; tmpc2 &lt;= '1' when st2,<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; '0' when others;<br>
with next_state select<br>
&nbsp; &nbsp; tmpc3 &lt;= '1' when st3,<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; '0' when others;<br>
process (clock_main , rst)&nbsp; &nbsp;<br>
begin<br>
if (rst = '1') then&nbsp; &nbsp; --异步复位<br>
&nbsp; &nbsp;&nbsp;&nbsp;pres_state &lt;= st0 ;<br>
&nbsp; &nbsp;&nbsp; &nbsp;c0&lt;='0';<br>
&nbsp; &nbsp;&nbsp; &nbsp;c1&lt;='0';<br>
&nbsp; &nbsp;&nbsp; &nbsp;c2&lt;='0';<br>
&nbsp; &nbsp;&nbsp; &nbsp;c3&lt;='0';<br>
elsif (clock_main'event and clock_main= '1') then<br>
&nbsp; &nbsp;&nbsp; &nbsp;pres_state &lt;= next_state ;<br>
&nbsp; &nbsp;&nbsp; &nbsp;c0&lt;=tmpc0;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;----将存储在输出寄存器的数据输出<br>
&nbsp; &nbsp;&nbsp; &nbsp;c1&lt;=tmpc1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;c2&lt;=tmpc2;<br>
&nbsp; &nbsp;&nbsp; &nbsp;c3&lt;=tmpc3;<br>
end if ;<br>
end process ;<br>
end rtl ;<br>
<br>
觉得这个方法管用或者你能从中学到点什么的话，请给我评分
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longt 发表于 2010-6-26 14:04:37

事实上对于楼主的第一个程序采用one-hot编码的话，那就是最优的程序，延时也最小（每一个编码的其中一位正好是一个输出）。之所以会有半个周期的延时，是和器件的性能有关的。<br>
<br>
我给的方法在输出逻辑比较复杂时有用。

ANG 发表于 2010-6-26 15:25:46

http://www.edacn.net/bbs/viewthr ... &amp;extra=page%3D1

Sunlife 发表于 2015-6-25 09:59:00

建议状态机用时钟沿触发～！

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