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CTT 发表于 2010-6-26 01:29:18

Verilog编个小东西 仿真的疑问

本帖最后由 fpgaw 于 2010-7-16 12:58 编辑

学着用Verilog编个小东西，但是仿真的时候跳出来数百个相同的警告：

Warning: Found glitch at time 120.0 ns of duration 120.0 ns on node "|usbtocpld|data~7"
Warning: Found glitch at time 120.0 ns of duration 120.0 ns on node "|usbtocpld|data~6"
...............................
最后还有三个错误：
Error: Logic level 0000000010100000 does not match expected logic level 0000000000000000 for node "out" at time 100.0 ns
Error: Logic level 00000000X0XXXXXX does not match expected logic level 0000000000000000 for node "out" at time 200.0 ns
Error: Logic level 00000000X0XXXXXX does not match expected logic level 0000000000000000 for node "out" at time 245.0 ns

哪位高手帮我解答一下啊？谢谢了。

ANG 发表于 2010-6-26 02:59:59

把源程序拿出来看看啊

ANG 发表于 2010-6-26 03:48:43

你的设计是实现什么东西啊 ？你仿真用的什么工具

AAT 发表于 2010-6-26 05:27:43

说的详细点

VVC 发表于 2010-6-26 05:48:16

不明白，太糊涂

ANG 发表于 2010-6-26 06:50:10

源程序是做什么的

longtime 发表于 2010-6-26 08:41:02

这样可能很难看的明白吧。。。。。。。。。

CTT 发表于 2010-6-26 08:46:15

module signal_gene(pwm,indata,q_out2,clk,WE,Flaut);<br>
&nbsp; &nbsp; input&nbsp; &nbsp; pwm;<br>
&nbsp; &nbsp; input&nbsp; &nbsp; indata;<br>
&nbsp; &nbsp; input&nbsp; &nbsp; clk;<br>
&nbsp; &nbsp; input&nbsp; &nbsp; WE;<br>
&nbsp; &nbsp; input&nbsp; &nbsp; Flaut;<br>
&nbsp; &nbsp; &nbsp; &nbsp; output&nbsp; &nbsp; q_out2;<br>
&nbsp; &nbsp; &nbsp; &nbsp; reg&nbsp; &nbsp;&nbsp; &nbsp; q_out2;<br>
&nbsp; &nbsp; &nbsp; &nbsp; reg&nbsp; &nbsp;&nbsp; &nbsp; q_out;<br>
&nbsp; &nbsp; &nbsp; &nbsp; reg&nbsp; &nbsp;&nbsp; &nbsp; data;<br>
&nbsp; &nbsp; &nbsp; &nbsp; reg&nbsp; &nbsp;&nbsp; &nbsp; p_in;<br>
&nbsp; &nbsp; &nbsp; &nbsp; reg&nbsp; &nbsp;&nbsp; &nbsp; q_out1;<br>
&nbsp; &nbsp; &nbsp; &nbsp; reg&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; i;<br>
&nbsp; &nbsp; &nbsp; &nbsp; reg&nbsp; &nbsp;&nbsp; &nbsp; count;<br>
&nbsp; &nbsp; &nbsp; &nbsp; //reg&nbsp; &nbsp;&nbsp; &nbsp; count1;<br>
&nbsp; &nbsp; &nbsp; &nbsp; //reg&nbsp; &nbsp;&nbsp; &nbsp;j;<br>
&nbsp; &nbsp; &nbsp; &nbsp; //reg&nbsp;&nbsp; addr;<br>
&nbsp; &nbsp; &nbsp; &nbsp; //reg&nbsp;&nbsp; addr0;<br>
&nbsp; &nbsp; &nbsp; &nbsp; //reg&nbsp;&nbsp; count;<br>
&nbsp; &nbsp; &nbsp; &nbsp; <br>
&nbsp; &nbsp; &nbsp; &nbsp; /*initial<br>
&nbsp; &nbsp; &nbsp; &nbsp; begin<br>
&nbsp; &nbsp; &nbsp; &nbsp; j=1;<br>
&nbsp; &nbsp; &nbsp; &nbsp; q_out1=12'h663;<br>
&nbsp; &nbsp; &nbsp; &nbsp; end*/<br>
/*initial <br>
begin<br>
data=0;<br>
end&nbsp; &nbsp; &nbsp; &nbsp; */<br>
<br>
always @(posedge clk)<br>
begin<br>
if(WE==0) data=indata;<br>
if(Flaut==0) data=0;<br>
p_in=data;<br>
p_in=pwm;<br>
case(p_in)<br>
10'b0000000000: q_out=12'b000000000000;//000<br>
10'b0000000001: q_out=12'b000000000000;//000<br>
10'b0000000011: q_out=12'b000000000000;//000<br>
10'b000000111: q_out=12'b000000000000;//000<br>
//正转<br>
//1 1 1.1扇区<br>
&nbsp; &nbsp;10'b0000001000: q_out=12'b011001100011;//001<br>
&nbsp; &nbsp;10'b0000001001: q_out=12'b011001100110;//000<br>
&nbsp; &nbsp;10'b0000001011: q_out=12'b110001100110;//-100<br>
&nbsp; &nbsp;10'b0000001111: q_out=12'b110011000110;//-1-10<br>
endcase<br>
end<br>
endmodule<br>
<br>
出现Warning: Found glitch at time 19640.0 ns of duration 20.0 ns on node "|signal_gene|clk"

CHA 发表于 2010-6-26 09:30:03

哎，没用过，帮你******
        http://bbs.vibesic.com/images/smilies/default/loveliness.gif

CTT 发表于 2010-6-26 11:19:46

只用过vhdl.... 帮不上了

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