longt 发表于 2010-6-26 00:59:42

dff和latch的区别？指得是QUARTUS2下，ALTERA提供得这两个模块有什么区别？？

本帖最后由 fpgaw 于 2010-11-15 11:01 编辑

dff和lantch的区别么？？
我指得是QUARTUS2下，ALTERA提供得这两个模块有什么区别？？

longt 发表于 2010-6-26 02:29:21

dff is edge sensitive, latch is level sensitive. actually, dff is comprised of two latch just like this<br>
<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;______&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; ______<br>
in ---|&nbsp; &nbsp;lacth |------|&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;|--------out<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;|&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;|&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;| latch&nbsp;&nbsp;|<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;|______|&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;|_____ | <br>
clk_____|___not_____|<br>
<br>
i am not sure whether you understand the drawing above <br>
there are many discussion in this web,you can serch them all.

CHANG 发表于 2010-6-26 03:15:04

谢谢，，<br>
我对这两个分别做了仿真，<br>
感觉一个LATCH比一个DFF要延时多一些。<br>
<br>
但是在比较复杂的系统（比如频率计中的计数器）把DFF换成LATCH，则仿真时的计数器是无法正确计数的。<br>
（我的改法是在HDL语言中把上升延触发改为高电平触发）

CTT 发表于 2010-6-26 03:27:18

谢谢,学习了!

encounter 发表于 2010-6-26 04:41:24

&gt;但是在比较复杂的系统（比如频率计中的计数器）把DFF换成LATCH，<br>
&gt;则仿真时的计数器是无法正确计数的。<br>
&gt;我的改法是在HDL语言中把上升延触发改为高电平触发）<br>
<br>
It surely did not work correctly. <br>
In a DFF, the output is latch at the edge of the clock. In a latch, the output follows the input as long as the enable signal is at a high(or low) level.<br>
I would suggest you read a basic digital design book.

tim 发表于 2010-6-26 05:30:42

谢谢，学习了

encounter 发表于 2010-6-26 06:52:43

基础要扎实

longtime 发表于 2010-6-26 07:01:08

latch在电平有效时是透明的，dff是边沿出发的

tim 发表于 2010-6-26 07:37:29

确实是很搞的两个概念，要区分好！！

CCIE 发表于 2010-6-26 08:56:59

latch要避免用，电平触发容易受干扰，产生误操作<br>
但是如果数据晚于时钟到达又不想等下个时钟就只能用latch，不过最好还是不要这么设计巴
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