longt 发表于 2010-6-28 11:50:23

无语，随便搜一下，满地都是！

FFT 发表于 2010-6-28 12:02:54

占空比1/3  2/3的很简单  50%的就比较复杂了 论坛里有50%的

VVC 发表于 2010-6-28 12:23:26

module (clkin,clkout,reset)<br>
input clkin;<br>
input reset;<br>
output clkout;<br>
<br>
//internal signal<br>
reg cnt1;<br>
reg cnt2;<br>
reg clk_generate1;<br>
reg clk_generate2;<br>
always @(posedge clkin or posedge reset)<br>
begin<br>
&nbsp;&nbsp;if (reset)<br>
&nbsp; &nbsp;begin<br>
&nbsp; &nbsp;&nbsp;&nbsp;cnt&lt;=0;<br>
&nbsp; &nbsp;&nbsp;&nbsp;clk_generate&lt;=0;<br>
&nbsp; &nbsp;end<br>
&nbsp;&nbsp;else<br>
&nbsp; &nbsp;&nbsp;&nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp; if (cnt==2)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;cnt&lt;=0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;clk_generate1&lt;=1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;end<br>
&nbsp; &nbsp;&nbsp; &nbsp;else <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;cnt&lt;=cnt+1;<br>
end<br>
<br>
always @(negedge clk or negedge reset)<br>
begin<br>
if(~reset)<br>
&nbsp; &nbsp;&nbsp;&nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; cnt2&lt;=0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; clk_gererate2&lt;=0;<br>
&nbsp; &nbsp; end<br>
else if(cnt2==2)<br>
&nbsp; &nbsp;&nbsp;&nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;cnt&lt;=0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;clk_generate2&lt;=1;<br>
&nbsp; &nbsp;&nbsp;&nbsp;end<br>
else<br>
&nbsp; &nbsp;&nbsp;&nbsp;cnt2&lt;=cnt2+1;<br>
end<br>
<br>
assign clkout=clk_generate1&amp;clk_generate2;<br>
endmodule<br>
<br>
这段程序貌似可以实现占空比为50％的分频，但是由于中间使用了clk的上升沿和下降沿两个不同的时钟特性，<br>
估计在做时序分析时回有问题。

ICE 发表于 2010-6-28 13:12:47

module (clkin,clkout,reset)<br>
input clkin;<br>
input reset;<br>
output clkout;<br>
<br>
//internal signal<br>
reg cnt1;<br>
reg cnt2;<br>
reg clk_generate1;<br>
reg clk_generate2;<br>
always @(posedge clkin or posedge reset)<br>
begin<br>
&nbsp;&nbsp;if (reset)<br>
&nbsp; &nbsp;begin<br>
&nbsp; &nbsp;&nbsp;&nbsp;cnt&lt;=0;<br>
&nbsp; &nbsp;&nbsp;&nbsp;clk_generate&lt;=0;<br>
&nbsp; &nbsp;end<br>
&nbsp;&nbsp;else<br>
&nbsp; &nbsp;&nbsp;&nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp; if (cnt==2)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;cnt&lt;=0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;clk_generate1&lt;=1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;end<br>
&nbsp; &nbsp;&nbsp; &nbsp;else <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;cnt&lt;=cnt+1;<br>
end<br>
<br>
always @(negedge clk or posedge reset)<br>
begin<br>
if(reset)<br>
&nbsp; &nbsp;&nbsp;&nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; cnt2&lt;=0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; clk_gererate2&lt;=0;<br>
&nbsp; &nbsp; end<br>
else if(cnt2==2)<br>
&nbsp; &nbsp;&nbsp;&nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;cnt&lt;=0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;clk_generate2&lt;=1;<br>
&nbsp; &nbsp;&nbsp;&nbsp;end<br>
else<br>
&nbsp; &nbsp;&nbsp;&nbsp;cnt2&lt;=cnt2+1;<br>
end<br>
<br>
assign clkout=clk_generate1&amp;clk_generate2;<br>
endmodule<br>
<br>
这段程序貌似可以实现占空比为50％的分频，但是由于中间使用了clk的上升沿和下降沿两个不同的时钟特性，<br>
估计在做时序分析时回有问题。

encounter 发表于 2010-6-28 13:55:20

错了，应该是：assign clkout=clk_generate1||clk_generate2;

CHA 发表于 2010-6-28 15:30:50

自己用计数器编一个，很easy的

ups 发表于 2010-6-28 16:31:58

对，可以用计数器编写，占空比得自己考虑了

CTT 发表于 2010-6-28 17:50:40

我有VHDL的任意N进制的半占空比分频器代码，自己写的已经通过了硬件测试，不只有兴趣没

UFO 发表于 2010-6-28 18:43:57

看不懂啊！！！！！！

usd 发表于 2010-6-28 19:28:35

bucuoa&nbsp;&nbsp;woxihuang
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