程序如下:
library ieee;
use ieee.std_logic_1164.all;
entity m_sequence1 is
port ( clk : in std_logic;
V : out bit_vector(0 to 3));
end m_sequence1;
architecture behave of m_sequence1 is
signal q: bit_vector(0 to 3):="0001";
begin
process (clk)
begin
if clk'event and clk='1' then
q<= q sll 1;
END IF;
v<=q;
END PROCESS;
END BEHAVE;