急问verilong的时序问题（附程序）

输入为a,b,c;输出为d。当a的上跳沿，b的 下跳沿，c的上跳沿时，d发生翻转，d的初始状态是高电平。我写了一段verilog的程序，不过好像有点问题，请大家帮我看看
module vb(d,a,b,c,clk,reset)
input a,b,c,clk,reset;
output reg d;
reg a1,a2,b1,b2,c1,c2

always@(posedge clk)
begin
  a1<=a; b1<=b; c1=c;
  a2<=a1;b2<=b1;c2<=c1;
end

always@(posedge reset or posedge clk)
  if(reset)d<=1;        
  else if(~a2 & a1 | b2 & ~b1 |~c2 & c1) d=~d;
endmodule

  TOP

else if((~a2 & a1) | (b2 & ~b1) |(~c2 & c1)) d=~d;

else if((~a2 & a1) | (b2 & ~b1) |(~c2 & c1)) d=~d