大家帮忙看下，程序的第三路输出，会有毛刺，别的路都好，是怎么回事

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.All;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY contrg IS
PORT(
      en:IN STD_LOGIC_VECTOR(13 DOWNTO 0);
      trigger:IN STD_LOGIC_VECTOR(13 DOWNTO 0);
      q:OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
      );
END contrg;

ARCHITECTURE rtl of contrg IS
---元件说明
COMPONENT trigger15_2
  PORT(
       trigger2,en2:IN STD_LOGIC;
       q2:OUT STD_LOGIC;
       enout2:OUT STD_LOGIC);
END COMPONENT;
COMPONENT trigger15_3
  PORT(
       trigger3,en3,en3_1:IN STD_LOGIC;
       q3:OUT STD_LOGIC;
       enout3:OUT STD_LOGIC);
END COMPONENT;
COMPONENT trigger15_4
  PORT(
       trigger4,en4,en4_1:IN STD_LOGIC;
       q4:OUT STD_LOGIC;
       enout4:OUT STD_LOGIC);
END COMPONENT;
COMPONENT trigger15_5
  PORT(
       trigger5,en5,en5_1:IN STD_LOGIC;
       q5:OUT STD_LOGIC;
       enout5:OUT STD_LOGIC);
END COMPONENT;
COMPONENT trigger15_6
  PORT(
       trigger6,en6,en6_1:IN STD_LOGIC;
       q6:OUT STD_LOGIC;
       enout6:OUT STD_LOGIC);
END COMPONENT;
signal enout:STD_LOGIC_VECTOR(13 DOWNTO 0);
---元件例化
begin
CONTRG2:trigger15_2
   PORT MAP(
            en2=>en(0),
            trigger2=>trigger(0),
            q2=>q(0),
            enout2=>enout(0)
            );
CONTRG3:trigger15_3
   PORT MAP(
            en3=>en(1),
            en3_1=>enout(0),
            trigger3=>trigger(1),
            q3=>q(1),
            enout3=>enout(1)
            );
CONTRG4:trigger15_4
   PORT MAP(
            en4=>en(2),
            en4_1=>enout(1),
            trigger4=>trigger(2),
            q4=>q(2),
            enout4=>enout(2)
            );
CONTRG5:trigger15_5
   PORT MAP(
            en5=>en(3),
            en5_1=>enout(2),
            trigger5=>trigger(3),
            q5=>q(3),
            enout5=>enout(3)
            );
CONTRG6:trigger15_6
   PORT MAP(
            en6=>en(4),
            en6_1=>enout(3),
            trigger6=>trigger(4),
            q6=>q(4),
            enout6=>enout(4)
            );
CONTRG7:trigger15_6
   PORT MAP(
            en6=>en(5),
            en6_1=>enout(4),
            trigger6=>trigger(5),
            q6=>q(5),
            enout6=>enout(5)
            );
CONTRG8:trigger15_6
   PORT MAP(
            en6=>en(6),
            en6_1=>enout(5),
            trigger6=>trigger(6),
            q6=>q(6),
            enout6=>enout(6)
            );
CONTRG9:trigger15_6
   PORT MAP(
            en6=>en(7),
            en6_1=>enout(6),
            trigger6=>trigger(7),
            q6=>q(7),
            enout6=>enout(7)
            );
CONTRG10:trigger15_6
   PORT MAP(
            en6=>en(8),
            en6_1=>enout(7),
            trigger6=>trigger(8),
            q6=>q(8),
            enout6=>enout(8)
            );
CONTRG11:trigger15_6
   PORT MAP(
            en6=>en(9),
            en6_1=>enout(8),
            trigger6=>trigger(9),
            q6=>q(9),
            enout6=>enout(9)
            );
CONTRG12:trigger15_6
   PORT MAP(
            en6=>en(10),
            en6_1=>enout(9),
            trigger6=>trigger(10),
            q6=>q(10),
            enout6=>enout(10)
            );
CONTRG13:trigger15_6
   PORT MAP(
            en6=>en(11),
            en6_1=>enout(10),
            trigger6=>trigger(11),
            q6=>q(11),
            enout6=>enout(11)
            );
CONTRG14:trigger15_6
   PORT MAP(
            en6=>en(12),
            en6_1=>enout(11),
            trigger6=>trigger(12),
            q6=>q(12),
            enout6=>enout(12)
            );
CONTRG15:trigger15_6
   PORT MAP(
            en6=>en(13),
            en6_1=>enout(12),
            trigger6=>trigger(13),
            q6=>q(13),
            enout6=>enout(13)
            );
END rtl;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.All;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY trigger15_2 IS
PORT(trigger2,en2:IN STD_LOGIC;
      q2:OUT STD_LOGIC;
      enout2:OUT STD_LOGIC);
END trigger15_2;

ARCHITECTURE BEH of trigger15_2 IS
  signal q:STD_LOGIC:='0';
  signal count2:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
BEGIN
  PROCESS(trigger2,en2)
   BEGIN
   IF(en2='0')THEN count2<="000";q<='0';
   ELSIF(trigger2 'EVENT AND trigger2='1')THEN
     IF(en2='1')THEN
     count2<=count2+1;
     END IF;
   END IF;
   IF(count2="101")THEN
     q<='1';
   END IF;
  END PROCESS;
q2<=q;
enout2<='1' WHEN count2="101" AND q='1' ELSE '0';
END BEH;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.All;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY trigger15_3 IS
PORT(trigger3,en3,en3_1:IN STD_LOGIC;
      q3:OUT STD_LOGIC;
      enout3:OUT STD_LOGIC);
END trigger15_3;

ARCHITECTURE BEH of trigger15_3 IS
  signal q:STD_LOGIC:='0';
  signal count3:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
BEGIN
  PROCESS(trigger3,en3)
   BEGIN
   IF(en3='0')THEN count3<="000";q<='0';
   ELSIF(trigger3 'EVENT AND trigger3='1')THEN
     IF(en3='1' AND en3_1='1')THEN
     count3<=count3+1;
     END IF;
   END IF;
   IF(count3="100")THEN
     q<='1';
   END IF;
  END PROCESS;
q3<=q;
enout3<='1' WHEN count3="101" AND q='1' ELSE '0';
END BEH;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.All;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY trigger15_4 IS
PORT(trigger4,en4,en4_1:IN STD_LOGIC;
      q4:OUT STD_LOGIC;
      enout4:OUT STD_LOGIC);
END trigger15_4;

ARCHITECTURE BEH of trigger15_4 IS
  signal q:STD_LOGIC:='0';
  signal count4:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
BEGIN
  PROCESS(trigger4,en4)
   BEGIN
   IF(en4='0')THEN count4<="000";q<='0';
   ELSIF(trigger4 'EVENT AND trigger4='1')THEN
     IF(en4='1' AND en4_1='1')THEN
     count4<=count4+1;
     END IF;
   END IF;
   IF(count4="011")THEN
     q<='1';
   END IF;
  END PROCESS;
q4<=q;
enout4<='1' WHEN count4="101" AND q='1' ELSE '0';
END BEH;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.All;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY trigger15_5 IS
PORT(trigger5,en5,en5_1:IN STD_LOGIC;
      q5:OUT STD_LOGIC;
      enout5:OUT STD_LOGIC);
END trigger15_5;

ARCHITECTURE BEH of trigger15_5 IS
  signal q:STD_LOGIC:='0';
  signal count5:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
BEGIN
  PROCESS(trigger5,en5)
   BEGIN
   IF(en5='0')THEN count5<="000";q<='0';
   ELSIF(trigger5 'EVENT AND trigger5='1')THEN
     IF(en5='1' AND en5_1='1')THEN
     count5<=count5+1;
     END IF;
   END IF;
   IF(count5="010")THEN
     q<='1';
   END IF;
  END PROCESS;
q5<=q;
enout5<='1' WHEN count5="101" AND q='1' ELSE '0';
END BEH;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.All;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY trigger15_6 IS
PORT(trigger6,en6,en6_1:IN STD_LOGIC;
      q6:OUT STD_LOGIC;
      enout6:OUT STD_LOGIC);
END trigger15_6;

ARCHITECTURE BEH of trigger15_6 IS
  signal q:STD_LOGIC:='0';
  signal count6:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
BEGIN
  PROCESS(trigger6,en6)
   BEGIN
   IF(en6='0')THEN count6<="000";q<='0';
   ELSIF(trigger6 'EVENT AND trigger6='1')THEN
     IF(en6='1' AND en6_1='1')THEN
     count6<=count6+1;
     END IF;
   END IF;
   IF(count6="001")THEN
     q<='1';
   END IF;
  END PROCESS;
q6<=q;
enout6<='1' WHEN count6="101" AND q='1' ELSE '0';
END BEH;

回复 1# oliviagx


    这是对波形仿真图中毛刺放大后的试图，如果把第三路换成第四个方波或第二个方波上升沿触发，就不会出现毛刺