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本帖最后由 oliviagx 于 2011-4-12 22:54 编辑
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.All;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY trigger15_6 IS
PORT(trigger6,en6,en6_1,clk:IN STD_LOGIC;
q6:OUT STD_LOGIC;
enout6:OUT STD_LOGIC);
END trigger15_6;
ARCHITECTURE BEH of trigger15_6 IS
signal q:STD_LOGIC:='0';
signal count6:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
signal count:STD_LOGIC_VECTOR(19 DOWNTO 0);
BEGIN
PROCESS(trigger6,en6)
BEGIN
IF(en6='0')THEN count6<="000";q<='0';
ELSIF(trigger6 'EVENT AND trigger6='1')THEN
IF(en6='1' AND en6_1='1')THEN
count6<=count6+1;
IF(count6="000")THEN
q<='1';
END IF;
END IF;
END IF;
END PROCESS;
holdtimeROCESS(clk,en6)
BEGIN
IF(en6='0')THEN count<=(OTHERS=>'0');
ELSIF(clk 'EVENT AND clk='1') THEN
IF(q='1')THEN
count<=count+'1';
END IF;
END IF;
END PROCESS;
q6<='1' WHEN count>="00000000000000001111" ELSE '0';
enout6<='1' WHEN count6="101" AND q='1' ELSE '0';
END BEH;
宏观上看输出正确,只是不知道为何对输出信号延时15个时钟周期,输出及输出使能就都有毛刺产生,毛刺对后续电路会有影响么 |
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