怎样利用VHDL语言实现除法功能？

怎样利用VHDL语言实现除法功能？  
我是一名初学者，请问怎样利用VHDL语言实现除法功能？
问题补充: 能够实现出现浮点数

回复 1# 小泡泡


    LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;
ENTITY CHUFA IS
GENERIC(bit_b:integer:=21;bit:integer:=21);
PORT(CLK:IN STD_LOGIC;
BEICHUSHU_bcd:IN integer range 2097150 downto 0;--BIT_B-1
CHUSHU_bcd:IN integer range 2097150 downto 0;--BIT-1
SHANG_bcd:OUT integer range 2097150 downto 0);--BIT_B-1
END CHUFA;
ARCHITECTURE chufa OF CHUFA IS
SIGNAL DIV:STD_LOGIC_VECTOR(BIT DOWNTO 0);--CHUSHU'LENGTH+1==BIT
SIGNAL BEICHUSHU: STD_LOGIC_VECTOR(BIT_B-1 DOWNTO 0);--BIT_B-1
SIGNAL CHUSHU: STD_LOGIC_VECTOR(BIT-1 DOWNTO 0);--BIT-1
SIGNAL SHANG: STD_LOGIC_VECTOR(BIT_B-1 DOWNTO 0);
BEGIN
BEICHUSHU=DIV THEN
SHANG(I)'0');
END PROCESS;
END chufa;

              楼上那是什么。