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verilog 综合时候出现erro xst 899 高手帮帮忙啊!不胜感激!

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ranbiage 发表于 2011-4-25 19:40:27 | 显示全部楼层 |阅读模式
本帖最后由 ranbiage 于 2011-4-25 19:44 编辑

module ss(
    input sys_clk,
    input rst_in_n,
    input rx_clk,
    input rx_en,
    input [3:0] rx_data,
    output reg rxd_en=1'b0,
    output reg rxd_valid=1'b0,
    output reg [7:0] rxd=8'b0
    );         
   
         reg [3:0] state;
         reg cnt=1'b0;
       
         parameter idle=4'b0001;
         parameter state1=4'b0010;
         parameter state2=4'b0100;
         parameter state3=4'b1000;
         
    always @(posedge sys_clk or posedge rx_clk)
           case(state)
             idle:
                    if(!rst_in_n)
                      begin
                      rxd_en<=1'b0;
                 rxd_valid<=1'b0;
                 rxd<=8'b0;
                      end
                    else state<=state1;
                  state1:
                    if(rx_en)
                      begin
                      rxd_en<=1'b1;
                      rxd_valid<=1'b1;
                      rxd[3:0]<=rx_data;
                                state<=state2;
                      end
                         else
                           state<=idle;
                  state2:
                    if(rx_en)
                      begin
                      rxd[7:4]<=rx_data;
                      cnt<=~cnt;
                                state<=state3;
                      end  
                         else
                           state<=idle;
                  state3:
                    if(!cnt)
                           begin
                             rxd_en<=1'b0;
                                  rxd_valid<=1'b1;
                                  state<=state1;
                                end
                  default:
                     state<=idle;
                endcase

endmodule

综合错误提示:ERROR:Xst:899 - "ss.v" line 41: The logic for <rxd_en> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "ss.v" line 41: The logic for <rxd_valid> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "ss.v" line 41: The logic for <rxd[7]> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "ss.v" line 41: The logic for <rxd[6]> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "ss.v" line 41: The logic for <rxd[5]> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "ss.v" line 41: The logic for <rxd[4]> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "ss.v" line 41: The logic for <rxd[3]> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "ss.v" line 41: The logic for <rxd[2]> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "ss.v" line 41: The logic for <rxd[1]> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "ss.v" line 41: The logic for <rxd[0]> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "ss.v" line 41: The logic for <state> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "ss.v" line 41: The logic for <cnt> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
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