Intel® Stratix® 10 Secure Device Manager Provides three

Overview of the Intel Stratix 10 Secure Device Manager

Figure 1 provides a high level summary of the Intel Stratix 10
SDM functional blocks. Not all functions are discussed in
this white paper; refer to upcoming Intel Stratix 10 technical
documentation and the Intel Stratix 10 Advance Information
Brief(2) for additional detail.
The SDM is the point of entry to the FPGA for JTAG
commands and interfaces, as well as for device confguration
data (from flash, SD card, or through PCI Express* hard
IP). The frst component of confguration data that enters
the SDM is the confguration data and microcode for the
SDM itself, which is authenticated with one or more digital
signatures (see “Confguration Process” on page 5). Once
the SDM is confgured and the processors are released from
reset, the SDM block manages all Intel Stratix 10 FPGA or
SoC security and confguration functions. This management
occurs out of band from the user design, and does not affect
timing closure or any other parameters of logic design.
SDM-enabled security functions
New security features have been introduced with each
generation of FPGA and SoC products. Table 1 provides a
top-level overview of these features. Intel Stratix 10 FPGAs
continue to support these features, including bitstream
encryption and authentication, volatile and non-volatile key
storage, JTAG and test mode disable, and tamper detection
sensors and monitors (voltage and temperature).