Altera推荐的有符号的乘法器写法

Verilog HDL Signed Multiplier with Input and Output Registers (Pipelining = 2)

module signed_mult (out, clk, a, b);
output [15:0] out;
input clk;
input signed [7:0] a;
input signed [7:0] b;
reg signed [7:0] a_reg;
reg signed [7:0] b_reg;
reg signed [15:0] out;
wire signed [15:0] mult_out;
assign mult_out = a_reg * b_reg;
always @ (posedge clk)
begin
a_reg <= a;
b_reg <= b;
out <= mult_out;
end
endmodule

8位乘法器的代码

Altera推荐的有符号的乘法器写法

Altera推荐的有符号的乘法器写法

Altera推荐的有符号的乘法器写法

Altera推荐的有符号的乘法器写法

VHDL写法：
Process(clock) begin
  if rising_edge(clock) then
    product <= signed(a) * signed(b);
  end if;
End process;

乘法器可以这样直接写吗？有没有自己设计过乘法器的同学啊？