FPGA vhdl post-route 仿真问题

a VHDL files that implements the following algorithm:

O <= ((((A-3) * B) + C) * D) + 5) –D)
With the following additional restrictions:
4 < A < 2的16次-1
0 < B < 2的16次-1
0 < C < 2的16次-1
D = 2的N次 where 0 ≤ N ≤ 31
The design is behaviorally correct: you can verify this in simulation. However, your design has an
additional restriction: because of the speed of the data coming in, the clock period cannot exceed
5ns (i.e., a minimum frequency of 200MHz is required).

The objective of this task is to verify if this condition is met and, if not, to re-design the circuit to
meet the specifications. To verify the operation, you are to design a self-checking VHDL testbench.
Once the final system has been designed, you are to produce a description file for each component
of the design, including a description of its operation, timing diagrams, input restrictions, etc.

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    15:29:33 02/11/2010
-- Design Name:
-- Module Name:    algorithm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity algorithm is
    Port ( A : in  STD_LOGIC_VECTOR (15 downto 0);
           B : in  STD_LOGIC_VECTOR (15 downto 0);
           C : in  STD_LOGIC_VECTOR (15 downto 0);
           D : in  STD_LOGIC_VECTOR (31 downto 0);
                          CLK: in STD_LOGIC;
                          overflow: out STD_LOGIC;
           O : out  STD_LOGIC_VECTOR (63 downto 0));
end algorithm;

architecture Behavioral of algorithm is
        signal INT1 : std_logic_vector(15 downto 0);
        signal INT2 : std_logic_vector(31 downto 0);
        signal INT3 : std_logic_vector(32 downto 0);
        signal INT4 : std_logic_vector(63 downto 0);
        signal INT5 : std_logic_vector(64 downto 0);
        signal INT6 : std_logic_vector(63 downto 0);
        signal overflow1, overflow2: std_logic;
begin

        INT1 <= A - 3;
       
        INT2 <= INT1 * B;

        INT3 <= ('0' & INT2) + ("0000000000000" & C);

        overflow1 <= INT3(32);

        INT4 <= INT3(31 downto 0)*D;
       
        INT5 <= ('0' & INT4) + 5;
        overflow2 <= INT5(64);
       
        int4reg: process (CLK) is
        begin
                if (clk'event and clk = '1') then
                        INT6 <= INT5(63 downto 0) - D;
                end if;
        end process;
       
        O <= INT6;
        overflow <= overflow1 or overflow2;


end Behavioral;

以上是题目。求高人解答。
意思是要实现上面的表达式。
目前给的代码大概需要16ns才能计算出结果，现在需要5ns计算出结果。
我的思路是把 乘以D这里改成移位乘法，是因为D 是2的倍数，所以用移位来实现乘法比乘法器来实现会快很对。

不知道对不对，请高手解答，谢谢。
小弟很想把这个搞懂