-----4选1
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity project5 is
port(a,b,i0,i1,i2,i3:in std_logic;
data_outut std_logic);
end project5;
architecture set41 of project5 is
begin
process(a,b,i0,i1,i2,i3)
variable sel:integer range 0 to 3;
begin
sel:=0;
if a='1' then
sel:=sel+1;
end if;
if b='1' then
sel:=sel+2;
end if;
data_out<=i0 when sel=0 else
i1 when sel=1 else
i2 when sel=2 else
i3 when sel=3;
end process;
end set41;
---提示错误 Error: Peak virtual memory: 212 megabytes |