library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity test is
generic(N:integer:=255);
port(clk:in std_logic;
data:in integer range 0 to N;--需要分频的数据,
data_en:in std_logic;--要求与需要分频的数据,即data同步,高电平有效
q_hundredut integer range 0 to 2;
q_tenut integer range 0 to 9;
q_aut integer range 0 to 9;
q_enut std_logic--输出使能,高电平有效,此时输出百十个位数。即q_hundred,q_ten,q_a
);
end;
architecture behav of test is
signal data_p:integer range 0 to N;
signal data_en1,data_en2:std_logic;
signal data_en_p:std_logic;
signal step:std_logic_vector(4 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1')then
data_en1<=data_en;
end if;
end process;
process(clk)
begin
if(clk'event and clk='1')then
data_en2<=data_en1;
end if;
end process;
data_en_p<=data_en1 and(not data_en2);
process(clk)
begin
if(clk'event and clk='1')then
data_p<=data;
end if;
end process;
constant data_h:integer:=100;
constant data_t:integer:=10;
constant data_a:integer:=1;
variable d:integer range 0 to N;
variable i_h:integer range 0 to 2;
variable i_t:integer range 0 to 9;
variable i_a:integer range 0 to 9;
begin
if(clk'event and clk='1')then
case step is
when idle=>
i_h:=0;
i_t:=0;
i_a:=0;
q_en<='0';
if(data_en_p='1')then
step<=ready;
d:=data_p;
else
step<=idle;
d:=0;
end if;
when ready=>
if(d>=data_h)then
d:=d-data_h;
i_h:=i_h+1;
step<=ready;
else
step<=count_ten;
end if;
when count_ten=>
if(d>=data_t)then
d:=d-data_t;
i_t:=i_t+1;
step<=count_ten;
else
step<=count_a;
end if;
when count_a=>
if(d>=data_a)then
d:=d-data_a;
i_a:=i_a+1;
step<=count_a;
else
step<=result_out;
end if;
when result_out=>
q_hundred<=i_h;
q_ten<=i_t;
q_a<=i_a;
q_en<='1';
i_h:=0;
i_t:=0;
i_a:=0;
d:=0;
step<=idle;
when others=>
q_hundred<=0;
q_ten<=0;
q_a<=0;
q_en<='0';
i_h:=0;
i_t:=0;
i_a:=0;
d:=0;
step<=idle;
end case;
end if;
end process;