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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_signed.ALL;
ENTITY sum_cash IS
PORT(clk :IN std_logic;
rst :IN std_logic;
C10 :IN std_logic;
C50 :IN std_logic;
C100 :IN std_logic;
lock_out_entry :IN std_logic;
clear :IN std_logic;
RC10 :IN std_logic;
RC50 :IN std_logic;
RC100 :IN std_logic;
sum :OUT integer RANGE 0 TO 20;
sum_10 :INOUT integer RANGE -10 TO 15;
sum_50 :INOUT integer RANGE -10 TO 15;
sum_100 :INOUT integer RANGE -10 TO 15);
END sum_cash;
ARCHITECTURE Behavioral OF sum_cash IS
signal x : integer RANGE 0 TO 20;
BEGIN
x<= sum_10+5*sum_50+10*sum_100;
sum_cashROCESS:process (rst,clk,x,clear)
BEGIN
IF (x<21) THEN
sum <=x;
ELSE
sum<=20;
END IF;
IF (rst='1') THEN
sum_10 <=0;
sum_50 <=0;
sum_100 <=0;
ELSE
IF (clear='1') THEN
sum_10 <= 0;
sum_50 <= 0;
sum_100 <= 0;
--END IF;
else
IF (clk'event and clk='1') THEN
IF (lock_out_entry ='0') THEN
IF (C10='1') THEN
sum_10 <=sum_10 + 1;
END IF;
IF (C50='1') THEN
sum_50 <=sum_50 + 1;
END IF;
IF (C100='1') THEN
sum_100 <=sum_100 + 1;
END IF;
ELSE
IF (RC10='1') THEN
sum_10 <=sum_10-1;
END IF;
IF (RC50='1') THEN
sum_50 <=sum_50-1;
END IF;
IF (RC100='1') THEN
sum_100 <=sum_100-1;
END IF;
END IF;
END IF;
END IF;
end if;
END PROCESS ;
END Behavioral;
语法上没错误了,不过不知道你想实现啥! |
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