EDA软件巡礼1：Concept RTLvision PRO

EDA软件巡礼1：Concept RTLvision PRO

参考链接：        http://poqsoft.com/eda/339.html
                http://poqsoft.com/eda/page/2


Concept RTLvision 6.9.2 Win/Linux

Concept RTLvision PRO提供RTL的快速可视化，以便工程师可以轻松地了解和实现现有的代码元素，无论是在VHDL，Verilog还是System Verilog。
它不再可能从头开始执行所有ASIC和SoC设计：元素 先前的设计必须被重复使用，并且第三方IP块被非常频繁地嵌入。
但是了解第三方IP或遗留代码的RTL并不总是容易的，使得它耗费时间并且难以修改和集成到新的设计中。


Concept RTLvision 6.8.12/6.9.2 Win/Linux | 44.8 mb

Concept RTLvision PRO provides fast visualization of RTL, so that an engineer can easily understand, and implement existing code elements, whether in VHDL, Verilog or System Verilog.
It is no longer possible to carry out all ASIC and SoC designs from scratch: elements of previous designs have to be re-used and third party IP blocks are embedded very often.
But understanding the RTL for third party IP or legacy code is not always easy, making it time consuming and difficult to modify and integrate into the new design.

Language: English
Operating Systems: Windows 7/8.x/10.x 64bit

datasheet_rtlvisionpro.pdf
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datasheet_rtlvisionpro.pdf
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datasheet_rtlvisionpro.pdf

RTLvision® PRO：轻松理解、调试和集成RTL代码

随着芯片复杂性的增加，不再可能从头开始进行SoC设计；必须重复使用先前设计的RTL代码，并且通常嵌入第三方IP块。
但是，了解第三方IP或传统RTL代码的Verilog，VHDL或SystemVerilog代码并不总是很容易，这使得修改和将这些代码集成到新设计中非常耗时且难以实现。

• 即时RTL到原理图 - 快速RTL可视化使RTL代码元素和大型设计更易于理解，调试和修改
• 混合语言设计 - 支持SystemVerilog、Verilog和VHDL，满足当今复杂SoC设计的需求
• 带有源代码链接和原理图链接的集成波形查看器
• 交互式片段导航 -  Logic Cone Window仅显示关键电路部分和RTL代码链接
• 基于Tcl的API，用于用户定义的电气规则检查和定制
• 超快的RTL阅读器和直观的GUI  - 易于使用
•    在一个工具中的VHDL查看器、Verilog查看器和SystemVerilog查看器
• 智能RTL源代码窗口 -  RTL源代码窗口中的交互式“操作栏”允许智能和特定于上下文的源代码导航。
  

RTLvision® PRO: Understand, Debug, and Integrate RTL Code, Easily

With rising chip complexity it is no longer possible to carry out SoC designs from scratch; RTL code of previous designs have to be re-used and third party IP blocks are often embedded.
But understanding Verilog, VHDL or SystemVerilog code for third party IP or legacy RTL code is not always easy, making it time consuming and difficult to modify and integrate such code into the new design.

•  RTL to schematics on the fly – fast RTL visualization makes RTL code elements and large designs easier to understand, debug, and modify
•  Mixed language design – support for SystemVerilog, Verilog and VHDL matches the demands of today’s complex SoC designs
•  Integrated Waveform Viewer with source code link and schematic link
•  Interactive fragment navigation – Logic Cone Window displays just the critical circuit sections and links to the RTL code
•  Tcl based API for user-defined electrical rule checks and customization
•  Ultra fast RTL readers and intuitive GUI – for ease of use
•  VHDL viewer, Verilog viewer and SystemVerilog viewer in one tool
•  Smart RTL Source Code Window – the interactive "Action Bar" within the RTL Source Code Window allows smart and context specific source code navigation.
  

datasheet_rtlvisionpro.pdf

快速RTL查看器 -
        RTLvision PRO提供RTL的快速可视化，因此工程师可以轻松理解和优化代码元素，无论是VHDL、Verilog还是System Verilog。

时钟树提取 -
        当集成来自不同源的RTL代码元素时，时钟信号通常是问题的根源;
        RTLvision PRO自动提取和分析时钟树，并提供时钟网络和时钟域的即时视图。

超快速RTL读取器和片段查看 -
        RTLvision PRO可以读取HDL并动态显示底层电路，使工程师能够立即了解RTL描述的功能。
        为了加速调试，可以在逻辑锥窗口中以图形方式显示关键的RTL代码部分。
        工程师可以专注于该关键片段，并链接到原始RTL源代码，而不必担心其他不太重要的设计领域。

轻松的RTL检查 -
        轻松的语言检查可以改进对尚未正确定义IP构建块的不完整设计的处理。

波形查看器和信号跟踪 -
        RTLvision PRO带有完全集成的波形查看器，并支持源代码、原理图视图和波形窗口中的交互式信号跟踪。
        RTLvision PRO将VCD模拟数据编译成自己的高速格式，以加速波形浏览和信号跟踪。

文档 -
        RTLvision PRO的自动文档功能提供了新的、更改的和重复使用的RTL代码的详细设计文档（来自Verilog代码的原理图，来自VHDL代码的原理图，PDF导出，......）。

概览

特色                                                                                优点
快速RTL阅读器和原理图即时                                                图形表示使得理解，调试，更改和实现RTL代码变得更加容易
交互式图形片段导航仅显示RTL的关键片段                        能够识别并专注于片段使得更容易理解和更改RTL代码
自动时钟树和时钟域提取和可视化                                        更快地检测和解决时钟域问题
集成波形查看器                                                                波形查看器支持交互式信号跟踪
完全支持混合语言设计（SystemVerilog，Verilog，VHDL）        设计人员可以轻松开发和调试当今最复杂的异构ASIC和SoC设计
RTL到原理图                                                                Verilog查看器，VHDL查看器和SystemVerilog查看器集成在一个工具中，可以分析几乎任何来源的IP块
自动化设计文档                                                                可以轻松记录新的和重复使用的RTL代码
Tcl UserWare API                                                        允许与工具流程和规则检查的定义进行交互


Fast RTL Viewer –
        RTLvision PRO provides fast visualization of RTL, so that engineers can easily understand and optimize code elements, whether in VHDL, Verilog or System Verilog.

Clock Tree Extraction –
        Clock signals are often a source of problems when integrating RTL code elements from different sources;
        RTLvision PRO automatically extracts and analyzes clock trees and gives an immediate view of the clock network and clock domains.

Ultra Fast RTL Reader and Fragment Viewing –
        RTLvision PRO can read HDL and display the underlying circuits on the fly, providing the engineer with immediate understanding of functionality of the RTL description.
        To accelerate debugging, critical RTL code portions can be graphically displayed in the Logic Cone Window.
        An engineer can concentrate on that critical fragment, with links to the original RTL source code, while not bothering about other less important areas of the design.

Relaxed RTL Checking –
        Relaxed language checking allows improved handling of incomplete designs where IP building blocks are not yet properly defined.

Waveform Viewer and Signal Tracing –
        RTLvision PRO comes with a fully integrated waveform viewer and with support for interactive signal tracing in the source code, schematic view and waveform window.
        RTLvision PRO compiles VCD simulation data into its own high-speed format for accelerated waveform browsing and signal tracing.

Documentation –
        The automated documentation features of RTLvision PRO provide detailed design documentation of new, changed and re-used RTL code (schematics from Verilog code, schematics from VHDL code, PDF export, …).

Customization –
        To meet the needs of a specific chip design project or an organization’s own standards a Tcl based UserWare API allows the functionality of RTLvision PRO to be extended and tailored.
        Customers can use this API to easily perform company specific Electrical Rule Checks (ERC), and to interface RTLvision PRO with other tools.


At a Glance

FEATURE                                                                         BENEFITS
Fast RTL reader and schematics on the fly                                                        
                                                                                Graphical representations make it easier to understand, debug, change and implement RTL code
Interactive Graphic Fragment Navigation shows only critical fragments of the RTL        
                                                                                Being able to identify and concentrate on a fragment makes it easier to understand and change RTL code
Automatic clock tree and clock domain extraction and visualization                        
                                                                                Faster detection and resolution of clock domain problems
Integrated Waveform viewer                                                                                
                                                                                Waveform viewer supports interactive signal tracing
Full support for mixed language designs (SystemVerilog, Verilog, VHDL)                
                                                                                Designers can easily develop and debug today’s most complex heterogeneous ASIC and SoC designs
RTL to schematics                                                                                        
                                                                                Verilog viewer, VHDL viewer, and SystemVerilog viewer in one tool allows IP blocks from almost any source to be analyzed
Automated design documentation
                                                                                New and re-used RTL code can be documented easily
Tcl UserWare API
                                                                                Allows interfacing with tool flow and definition of rule checks

EDA软件巡礼之一：Concept RTLvision PRO

官网介绍

参考链接：http://www.concept.de/RTLvision.html

官网介绍

RTLvision  - 用于Verilog和VHDL的RTL调试器和查看器

RTLvision® PRO提供简单的RTL调试和RTL代码的快速可视化，使工程师可以轻松理解，实现和优化VHDL，Verilog或SystemVerilog代码。
请查看演示视频：基本功能和时钟树分析器。

随着芯片复杂性的提高，不再可能从头开始执行所有ASIC和SoC设计：必须重复使用先前设计的RTL代码元素，并且经常嵌入第三方IP模块。
但是，了解第三方IP或遗留代码的VHDL或Verilog源代码并不总是那么容易，这使得它非常耗时且难以修改并集成到新设计中。

所有RTL语言 - 一个调试驾驶舱 -  
        RTLvision PRO是一个功能强大且易于使用的RTL查看器，它将Verilog查看器、VHDL查看器和SystemVerilog查看器组合在一个集成的调试驾驶舱中。


RTLvision - RTL debugger and viewer for Verilog and VHDL

RTLvision® PRO provides easy RTL debugging and fast visualization of RTL code, so that engineers can easily understand, implement and optimize VHDL, Verilog or SystemVerilog code. Please check out the Demo Videos: Basic Features and Clock Tree Analyzer.

With rising chip complexity it is no longer possible to carry out all ASIC and SoC designs from scratch: RTL code elements of previous designs have to be re-used and third party IP blocks are embedded very often. But understanding VHDL or Verilog source code for third party IP or legacy code is not always easy, making it time consuming and difficult to modify and integrate into the new design.

All RTL Languages - One Debugging Cockpit — RTLvision PRO is a powerful easy to use RTL viewer who combines Verilog viewer, VHDL viewer and SystemVerilog viewer in one single integrated debugging cockpit.

官网介绍

• 了解高级设计：                快速Verilog和VHDL可视化使传统RTL代码和IP代码易于理解，调试，修改和集成
• 混合语言功能：                支持SystemVerilog，Verilog和VHDL，可满足当今复杂的异构ASIC和SoC设计的需求
• 交互式片段导航：                Logic Cone Window显示与原始源代码链接的RTL / HDL关键部分的可视化
• 基于Tcl的UserWare API：        访问数据库和GUI以进行项目特定或公司特定的定制
  

时钟树提取 -
        当集成来自不同源的RTL代码元素时，时钟信号通常是问题的根源;
        RTLvision PRO自动提取和分析时钟树，并提供时钟网络和时钟域的即时视图。

• Understand high-level designs:                 Fast Verilog and VHDL visualization makes legacy RTL code and IP code easy to understand, debug, modify and integrate
•         Mixed language capability:                 Support for SystemVerilog, Verilog and VHDL matches the demands of today's complex heterogeneous ASIC and SoC designs
•         Interactive fragment navigation:         Logic Cone Window displays a visualization of just critical sections of RTL/HDL linked to original source code
•         Tcl based UserWare API:                 access to database and GUI for project-specific or company-specific customization
  

Clock Tree Extraction —
        Clock signals are often a source of problems when integrating RTL code elements from different sources;
        RTLvision PRO automatically extracts and analyzes clock trees and gives an immediate view of the clock network and clock domains.

官网介绍

交互式RTL代码导航 -  
        RTLvision PRO可以读取HDL（硬件描述语言）并动态显示底层电路，使工程师能够立即了解RTL描述的功能。
        为了加速调试，可以在逻辑锥窗口中以图形方式显示关键代码部分：工程师可以专注于该关键片段，并链接到原始HDL源代码，同时不会打扰设计的其他区域。

波形查看器和信号跟踪 -  
        RTLvision PRO具有完全集成的波形查看器，并支持源代码，原理图视图和波形窗口中的交互式信号跟踪。
        RTLvision PRO将VCD模拟数据编译成自己的高速格式，以加速波形浏览和信号跟踪。


Interactive RTL code navigation —
        RTLvision PRO can read HDL (Hardware Description Language) and display the underlying circuits on the fly, providing the engineer with immediate understanding of functionality of the RTL description.
        To accelerate debugging, critical code portions can be graphically displayed in the Logic Cone Window: the engineer can concentrate on that critical fragment, with links to the original HDL source code, while not bothering about other areas of the design.

Waveform Viewer and Signal Tracing —
        RTLvision PRO comes with a fully integrated waveform viewer and with support for interactive signal tracing in the source code, schematic view and waveform window.
        RTLvision PRO compiles VCD simulation data into its own high-speed format for accelerated waveform browsing and signal tracing.