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本帖最后由 lcytms 于 2019-4-15 15:22 编辑
参考链接:https://www.bluepearlsoftware.com/learning-center/
Learning Center 学习中心
Datasheets 数据表
PDF Analyze RTL™ Suite 分析RTL™套件
PDF CDC Option CDC选项
PDF SDC Option SDC Option
PDF Advanced Clock Environment (ACE) 高级时钟环境(ACE)
PDF Management Dashboard 管理仪表板
White Papers 白皮书
PDF Accelerating Xilinx All Programmable FPGA and SoC Design Verification with Blue Pearl Software 使用Blue Pearl软件加速Xilinx全可编程FPGA和SoC设计验证
PDF Visual Verification Suite: User Defined Checks and Messages Visual Verification Suite:用户定义的检查和消息
PDF RTL Development And Testing For Medical Devices 医疗器械的RTL开发和测试
PDF Accelerating DO-254 Verification 加速DO-254验证
PDF Accelerated IP Development Using an Agile RTL Design Flow 使用敏捷RTL设计流程加速IP开发
PDF Visual Verification Suite Command Line Tcl Operation Visual Verification Suite命令行Tcl操作
PDF How Can We Build More Reliable EDA Software Whitepaper 如何构建更可靠的EDA软件白皮书
PDF RTL Analysis for Complex FPGA designs using a Grey Cell Methodology to Improve QoR 使用灰色单元方法提高QoR的复杂FPGA设计的RTL分析
PDF What is an RTL Tool Doing Next to ARM Embedded Software? RTL工具在ARM嵌入式软件旁边做什么?
PDF A Kaleidoscopic View of Finite State Machine Design 有限状态机设计的万花筒视图
PDF The Truth About Knowing Your False Paths 关于了解你的虚假路径的真相
Application Notes 应用笔记
PDF Blue Pearl Multi-cycle Path Detection Blue Pearl多循环路径检测
PDF Creating and Using Packages 创建和使用包
PDF Reduce Metastability by Using a User Grey CellTM Methodology for IP and FPGA Clock Domain Crossing Analysis 使用用户灰色CellTM方法降低IP和FPGA时钟域交叉分析的亚稳态性
Software Download 软件下载
Software Download 软件下载
Videos 视频
Analyzing Long Paths With Visual Verification Suite 使用Visual Verification Suite分析长路径
Clock Domain Crossing Challenges and Solutions (DAC 2017 Floor Presentation) 时钟域跨越挑战和解决方案(DAC 2017楼层演示)
What FPGA Vendor Tools Don’t Say About Your Design (DAC 2017 Floor Presentation) 什么FPGA供应商工具不说您的设计(DAC 2017楼层演示)
Creating and Delivering High Reliability RTL, Case Studies (DAC 2017, Floor Presentation) 创建和提供高可靠性RTL,案例研究(DAC 2017,现场演示)
DO-254 Verification with the Visual Verification Suite 使用Visual Verification Suite进行DO-254验证
Management Dashboard (For Managers, Viewer Mode) 管理仪表板(适用于经理,查看器模式)
Management Dashboard (For Engineers) 管理仪表板(适用于工程师)
Visual Verification Suite Examples and Tutorials Visual Verification Suite示例和教程
Visual Verification Suite Live Transcript Visual Verification Suite Live Transcript
Loading New Projects 加载新项目
Advanced Clock Environment 高级时钟环境
Why Create Timing Constraints? 为什么要创建时序约束?
Why Advanced Clock Environment (ACE) for CDC Analysis? 为什么高级时钟环境(ACE)用于CDC分析?
High Reliability FPGA Design for Space Applications 空间应用的高可靠性FPGA设计
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