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本帖最后由 lcytms 于 2019-2-24 10:13 编辑
参考链接：https://www.microsemi.com/produc ... ces/1751-libero-ide
官网介绍
Libero IDE
Microsemi的Libero®IDE软件版本可用于设计Microsemi Rad-Tolerant FPGA，Antifuse FPGA和Legacy＆Discontinued Flash FPGA，并管理从设计输入、综合和仿真到布局布线、时序和功耗分析的整个设计流程。
PCN 1108：Libero IDE中的硅系列支持。
对于其他系列，请使用Libero SoC Design Suite或Libero SoC PolarFire，有关详细信息，请参阅设备支持选项卡。
注意：Libero许可证选项正在更改，如客户通知CN17012中所示。
这些更改于2017年3月13日发布的Libero SoC v11.8生效。
Libero IDE软件功能：
强大的项目和设计流程管理
全套集成设计输入工具和方法：
SmartDesign图形SoC设计创建，自动抽象到HDL
IP核目录和配置
用户定义的块创建流程，用于设计重用
Synplify Pro ME综合完全优化了Microsemi FPGA器件性能和面积利用率
Synphony Model Compiler ME在Simulink®环境中执行高级综合优化
Modelsim ME VHDL或Verilog行为，后综合和布局后模拟功能
物理设计实施，布局规划，物理约束和布局
定时驱动和电源驱动的布局布线
SmartTime环境用于时序约束管理和分析
SmartPower为实际和“假设”功率方案提供全面的功率分析
与FlashPro程序员的接口
用于Microsemi闪存设计的路径上片上调试工具和识别ME调试软件
用于Microsemi反熔丝设计的Silicon Explorer II调试软件
Microsemi's Libero ® IDE software release for designing with Microsemi Rad-Tolerant FPGAs, Antifuse FPGAs and Legacy & Discontinued Flash FPGAs and managing the entire design flow from design entry, synthesis and simulation, through place-and-route, timing and power analysis. PCN 1108: Silicon Family Support in Libero IDE.
For other families please use Libero SoC Design Suite or Libero SoC PolarFire, see Device Support tab for details.
Note: Libero license options are changing as indicated in Customer Notification CN17012. These changes came into effect with Libero SoC v11.8 released on 13th March, 2017.
Libero IDE Software Features:
Powerful project and design flow management
Full suite of integrated design entry tools and methodologies:
SmartDesign graphical SoC design creation with automatic abstraction to HDL
IP Core Catalog and configuration
User-defined block creation flow for design re-use
Synplify Pro ME synthesis fully optimizes Microsemi FPGA device performance and area utilization
Synphony Model Compiler ME performs high-level synthesis optimizations within a Simulink® environment
Modelsim ME VHDL or Verilog behavioral, post-synthesis and post-layout simulation capability
Physical design implementation, floorplanning, physical constraints, and layout
Timing-driven and power-driven place-and-route
SmartTime environment for timing constraint management and analysis
SmartPower provides comprehensive power analysis for actual and "what if" power scenarios
Interface to FlashPro programmers
Post-route On Chip Debug Tools and Identify ME debugging software for Microsemi flash designs
Silicon Explorer II debugging software for Microsemi antifuse designs
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