如题:要在同一个进程里面判断两个时钟信号的上升沿,编译报错如下:
Error (10822): HDL error at deal_voice48.vhd(70): couldn't implement registers for assignments on this clock edge
进程中是要检测CLKIN和CLKOUT的上升沿,process中的敏感信号只添加了CLKIN
process(valid,valid_reg,prog_full,prog_full_reg)
begin
if (valid = '1' and valid_reg = '0') then
wr_en <= '1';
elsif (prog_full = '1' and prog_full_reg = '0') then
wr_en <= '0';
end if;
start_fft <= (not prog_full_reg) and prog_full ;
end process;
上面的valid_reg,prog_full_reg是valid,prog_full延迟一个周期的信号,就像这样
process(sysclk)
begin
if (rising_edge(sysclk)) then
valid_reg <= valid;
prog_full_reg <= prog_full;
end if;
end process;
上面的valid_reg,prog_full_reg是valid,prog_full延迟一个周期的信号,就像这样
process(sysclk)
begin
if (rising_edge(sysclk)) then
valid_reg <= valid;
prog_full_reg <= prog_full;
end if;
end process;