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- module diver(clk,div2,div4,div8);
- input clk;
- output div2,div4,div8;
- reg div2,div4,div8;
- reg [2:0]count;
- always@(posedge clk)
- begin
- count<=count+1;
- div2<=count[0];
- div4<=count[1];
- div8<=count[2];
- end
-
- endmodule
复制代码 testbench 文本- `timescale 1 ns/ 1 ps
- module diver_vlg_tst();
- // constants
- // general purpose registers
- reg eachvec;
- // test vector input registers
- reg clk;
- // wires
- wire div2;
- wire div4;
- wire div8;
- // assign statements (if any)
- diver i1 (
- // port map - connection between master ports and signals/registers
- .clk(clk),
- .div2(div2),
- .div4(div4),
- .div8(div8)
- );
- initial
- begin
- clk=0;
- forever
- #10 clk=~clk;
- #100;
- $stop;
-
- end
- endmodule
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