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文件1:TLV5618.v
module TLV5618
(
input CLK,
input nRST,
input [15:0]DA_Data,
input DA_Start_Sig,
output SCLK,
output DIN,
output DA_Done_Sig,
output CS
);
/*TLV5618数据格式 DA_Data[15:12]
D15 D14 D13 D12 D11~D0
R1 SPD PWR R0 12Data Bits
SPD:转换速度控制位
1:快速模式
0:慢速模式(上电默认)
PWR:电源控制位
1:省电模式
0:正常模式(上电默认)
R1,R0:寄存器选择位
00:写数据到B路和缓冲器
01:写数据到缓冲器
10:写数据到A路,同时使用缓冲器的数据 更新B路输出
11:保留
*/
parameter T5US=8'd50;//5us
reg [7:0]Count;
always @(posedge CLK or negedge nRST)
if( !nRST )
Count <= 8'd0;
else if( DA_Start_Sig & ( Count == T5US ) )
Count <= 8'd0;
else if( DA_Start_Sig )
Count <= Count + 1'b1;
else
Count <= 8'd0;
reg [ 5:0 ]i;
reg isDIN;
reg isSCLK;
reg isDone;
reg isCS;
always @( posedge CLK or negedge nRST )
if( !nRST )
begin
i <= 6'd0;
isSCLK <= 1'b0;
isDIN <= 1'b0;
isDone <= 1'b0;
isCS <= 1'b1;
end
else if( DA_Start_Sig )
case( i )
6'd0: begin isCS <= 1'b0; i <= i + 1'b1; end
1,3,5,7,9,11,13,15,
17,19,21,23,25,27,29,31:
if( Count == T5US )
i <= i + 1'b1;
else
begin
isSCLK <= 1'b0;
isDIN <= DA_Data[ 15 - (( i - 1'b1) >>1 ) ];
end
2,4,6,8,10,12,14,16,
18,20,22,24,26,28,30,32:
if( Count == T5US )
i <= i + 1'b1;
else
isSCLK <= 1'b1;
6'd33:
begin
isDone <= 1'b1;
isCS <= 1'b1;
i <= i + 1'b1;
end
6'd34: begin isDone <= 1'b0; i <= 6'd0; end
endcase
assign SCLK = isSCLK;
assign DIN =isDIN;
assign DA_Done_Sig = isDone;
assign CS =isCS;
endmodule
文件2:DA_Control_Module.v
module DA_Control_Module
(
input CLK,
input nRST,
input DA_Done_Sig,
output DA_Start_Sig,
output [ 15:0 ]DA_Data
);
reg [ 15:0 ]rDATA;
reg [ 4:0 ]i;
reg isStart;
always @( posedge CLK or negedge nRST )
if( !nRST )
begin
rDATA <= 16'd0;
i <= 5'd0;
end
else case( i )
5'd0:if( DA_Done_Sig ) begin isStart <= 1'b0; i <= i + 1'b1; end
else begin rDATA <= 16'b0100_1011_0111_0001; isStart <= 1'b1; end
5'd1: i <= 5'd1;
endcase
assign DA_Data = rDATA;
assign DA_Start_Sig = isStart;
endmodule
文件3:DA.v
module DA
(
input CLK,
input nRST,
output DIN,
output SCLK,
output CS
);
wire [ 15:0 ]DA_Data;
wire DA_Done_Sig;
wire DA_Start_Sig;
DA_Control_Module U1
(
.CLK( CLK ),
.nRST( nRST ),
.DA_Done_Sig( DA_Done_Sig ),
.DA_Start_Sig( DA_Start_Sig ),
.DA_Data( DA_Data )
);
TLV5618 U2
(
.CLK( CLK ),
.nRST( nRST ),
.DA_Data( DA_Data ),
.DA_Start_Sig( DA_Start_Sig ),
.SCLK( SCLK ),
.DIN( DIN ),
.DA_Done_Sig( DA_Done_Sig ),
.CS( CS )
);
endmodule
4.仿真
激励文件
`timescale 1 ns/ 1 ns
module DA_Simulation();
reg CLK;
reg nRST;
wire DIN;
wire SCLK;
wire CS;
DA I1
(
.CLK( CLK ),
.nRST( nRST ),
.SCLK( SCLK ),
.DIN( DIN ),
.CS( CS )
);
initial
begin
nRST = 1'b0;
#500
nRST = 1'b1;
CLK = 1'b1;
forever #100 CLK = ~CLK;
end
endmodule
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