输入管脚带有上拉电阻, 有时还需要外加上拉电阻, 他们的作用是什么?

输入管脚带有上拉电阻, 有时还需要外加上拉电阻, 他们的作用是什么?
答：The pull-up resistors built into the FPGA I/O pin are relatively weak - usually in the order of several tens of Kohm to a hundred Kohm.  It will be too slow if you rely on these weak pull-up to charge up an open-drain signal to logic '1'.  You can speed it up by adding a stronger external pull up resistor. （参考译文：置入FPGA I/O引脚的上拉电阻相对较弱, 通常为几十千欧至几百千欧. 如果依靠这些弱电阻来将开漏信号填充至逻辑“1”, 则速度会很慢. 通过添加外部上拉电阻可以提高速度. ）

上级芯片或模块和本级芯片或模块的时钟是异步时钟域的