vwerilog数据类型 常量 变量

常量：
&#160; &#160; &#160; &#160; 整数：<位宽 num'><进制 b|o|d|h><数字>，例如 4'b1010
&#160; &#160; &#160; &#160; x值(不定值)和z值(高阻值，也可用?代替)
&#160; &#160; &#160; &#160; &#160; &#160; x和z可以标识某一位或者某一个数字
&#160; &#160; &#160; &#160; &#160; &#160; 4'b10x0,4'bx,4'b101z,4'bz,4'b?
&#160; &#160; &#160; &#160; 负数：整数最前面加-
&#160; &#160; &#160; &#160; 下划线：分割数字部分，更加易读(8'b1000_1000)
&#160; &#160; 参数：parameter
&#160; &#160; &#160; &#160; parameter 参数名=表达式;
&#160; &#160; &#160; &#160; 表达式只能是数字或者定义过的参数
&#160; &#160; 变量：
&#160; &#160; &#160; &#160; wire型：wire [n-1:0] 数据名;
&#160; &#160; &#160; &#160; &#160; &#160; wire表示信号，常用来表示assign关键字指定的组合逻辑信号
&#160; &#160; &#160; &#160; &#160; &#160; wire型信号可以用作输入，输出
&#160; &#160; &#160; &#160; reg型：reg [n-1:0] 数据名;
&#160; &#160; &#160; &#160; &#160; &#160; 对存储单元的抽象
&#160; &#160; &#160; &#160; &#160; &#160; 常用来表示always模块内的指定信号，常代表触发器
&#160; &#160; &#160; &#160; &#160; &#160; always块内被赋值的每一个信号都必须定义为reg型
&#160; &#160; &#160; &#160; memory型：reg [n-1:0] 存储器名[m-1:0];
&#160; &#160; &#160; &#160; &#160; &#160; reg [n-1:0]表示基本存储单元的大小
&#160; &#160; &#160; &#160; &#160; &#160; 存储器名[m-1:0]表示基本存储单元的个数，存储空间的容量
&#160; &#160; &#160; &#160; &#160; &#160; 对存储器进行地址索引的表达式必须是常数表达式
&#160; &#160; &#160; &#160; &#160; &#160; 一个n位寄存器可以在一条赋值语句里进行赋值，而一个完整的存储器不行
&#160; &#160; 运算符及表达式：
&#160; &#160; &#160; &#160; 基本运算符：+ - * / %
&#160; &#160; &#160; &#160; 位运算符：~ & | ^ ^~
&#160; &#160; &#160; &#160; 逻辑运算符：&& || !
&#160; &#160; &#160; &#160; 关系运算符：< > <= >=
&#160; &#160; &#160; &#160; 等式运算符：== != (不管x、z，结果可能是不定值)
&#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; === !==(对参数的x、z都进行比较)
&#160; &#160; &#160; &#160; 移位运算符：<< >>
&#160; &#160; &#160; &#160; 位拼接运算符：{ }，将几个信号拼接起来，例如{a,b[3:0],w,3'b100}
&#160; &#160; &#160; &#160; 缩减运算符：C =&B;C =|B;C =^B;
&#160; &#160; &#160; &#160; 优先级别：和c语言差不多，加括号
&#160; &#160; 赋值语句：
&#160; &#160; &#160; &#160; 1)非阻塞赋值方式(b <= a)
&#160; &#160; &#160; &#160; &#160; &#160; a.块结束才完成赋值
&#160; &#160; &#160; &#160; &#160; &#160; b.b的值不是立刻就改变的
&#160; &#160; &#160; &#160; &#160; &#160; c.在可综合的模块中常用
&#160; &#160; &#160; &#160; 2)阻塞赋值方式(b = a)
&#160; &#160; &#160; &#160; &#160; &#160; a.赋值语句执行完成后，块才结束
&#160; &#160; &#160; &#160; &#160; &#160; b.b的值在赋值语句执行后立刻改变
&#160; &#160; &#160; &#160; &#160; &#160; c.可能会产生意想不到的结果
&#160; &#160; &#160; &#160; 简单理解：
&#160; &#160; &#160; &#160; &#160; &#160; 非阻塞赋值用了多个触发器，每次时钟到达，所有触发器都触发一次
&#160; &#160; &#160; &#160; &#160; &#160; 阻塞赋值连到同一个触发器上，时钟到达，导致所有寄存器被赋值
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verilog数据类型 常量 变量