实在不懂

这是一个关于ADC0809采样控制程序，由于才学vhdl所以看了半天没懂。特别是com:process(current_state,eoc) 此进程后面的语句。为什么要定义六个状态。哪位高手能帮帮我，谢谢。最好能详细讲解一下。谢谢谢谢额。。。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity PL_AD is
port ( d : in std_logic_vector(7 downto 0);
clk,eoc : in std_logic;
lock1,start, ale,en: out std_logic;
abc_in :in std_logic_vector(2 downto 0);
abc_out :std_logic_vector(2 downto 0);--ADC0809
q : out std_logic_vector(7 downto 0));
end pl_AD;
architecture behav of PL_AD is
type states is ( st0,st1, st2, st3, st4,st5,st6);
signal current_state, next_state:states:=st0;
signal regl :std_logic_vector(7 downto 0);
signal lock : std_logic;
signal qq:std_logic_vector(7 downto 0);
begin
com:process(current_state,eoc)
begin
case current_state is
when st0=>next_state<=st1;ale<='0';start<='0';en<='0';
when st1=>next_state<=st2;ale<='1';start<='0';en<='0';
when st2=>next_state<=st3;ale<='0';start<='1';en<='0';
when st3=> ale<='0';start<='0';en<='0';
if eoc='1' then next_state<=st3;
else next_state<=st4;
end if;
when st4=> ale<='0';start<='0';en<='0';
if eoc='0' then next_state<=st4;
else next_state<=st5;
end if;
when st5=>next_state<=st6;ale<='0';start<='0';en<='1';
when st6=>next_state<=st0;ale<='0';start<='0';en<='1';regl<=d;
when others=> next_state<=st0;ale<='0';start<='0';en<='0';
end case;
end process;
clock:process(clk)
begin
if clk'event and clk='1' then qq<=qq+1;
if QQ="01111111" THEN lock<='1'; current_state <=next_state;
elsif qq<="01111111" then lock<='0';
end if;
end if;
end process;
q<=regl; lock1<=lock; abc_out<=abc_in;
end behav;

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