entity Latch_p is
port(D:in std_logic;
ena:in std_logic;
Qut std_logic
);
end entity ;
architecture one of Latch_p IS
signal sig_save:std_logic;
begin
process (D,ena)
begin
if ena='1' then
sig_save<=D;
end if;
Q<=sig_save;
end process;
end architecture one;