不知这个能不能满足你的要求
library ieee;
use ieee.std_logic_1164.all;
entity counter20 is
port (clk:in std_logic;
rst:in std_logic;
y1ut std_logic;
y2ut std_logic
);
end counter20;
architecture hav of counter20 is
signal y1_temp:std_logic;
signal y2_temp:std_logic;
begin
y1<=y1_temp;
y2<=y2_temp;
process(clk,rst)
variable counter:integer range 0 to 1;
begin
if (rst='1') then
y1_temp<='0';
y2_temp<='0';
counter:=0;
else
if (clk'event and clk='1')then
if (counter=0)then
y1_temp<=not y1_temp;
counter:=counter+1;
elsif counter=1 then
y2_temp<=not y2_temp;
counter:=0;
end if;
end if;
end if;
end process;