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module buzzer (clk, rst_n, s);
input clk;
input rst_n;
output reg s;
//定参
`define Fclk 50_000_000
`define Fout 10000
`define CNT_NUM (`Fclk/`Fout)
reg [32:0] cnt;
//行为建模:计数器计数1ms
always @ (posedge clk, negedge rst_n) begin
if(rst_n ==1'b0) //计数器清零
cnt <= 16'd0; //计数器没有计数到1ms
else if (cnt <`CNT_NUM - 1'd1) //计数器自加一
cnt <= cnt + 16'd1; //计数器计数到1ms
else
cnt <= 16'd0; //计数器清零
end
//1ms周期中: 第一个0.5ms输出时钟位高电平, 第二个0.5ms输出时钟为低电平
always @ (posedge clk, negedge rst_n) begin
if (rst_n == 1'b0)
s <= 1'b1; //初始输出时钟为点平
else if(cnt < (`CNT_NUM / 2 -1'd1)) //计数器没有计数到0.5ms
s <= 1'b1; //拉高输出时钟
else
s <= 1'b0; //拉低输出时钟
end
endmodule
/*测试文件*/
`timescale 1ns/1ps
module buzzer_tb;
reg clk;
reg rst_n;
wire s;
buzzer buzzer_inst(
.clk(clk),
.rst_n(rst_n),
.s(s)
);
initial clk = 1'b1;
always #10 clk =~clk;
initial begin
rst_n = 1'b0;
#200.1
rst_n = 1'b1;
end
endmodule |
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