sram读写

实现功能：en=1时，data_lcd<=data_ram即从ram向lcd读数据；当en=0时，data_ram<=data_reg;从寄存器向ram写数据，读写数据控制信号和地址信号略去，只考虑数据信号，时序仿真时：found logic contention at XXns on node XX警告，时序仿真结果也不对，如图，本人新手，各位大侠指导下子程序如何改正。


library ieee;
use ieee.std_logic_1164.all;
entity sx is
port(en:in std_logic;
     data_reg:in std_logic_vector(7 downto 0);
     data_lcdut std_logic_vector(7 downto 0);
     data_ram:inout std_logic_vector(7 downto 0));
end sx;
architecture art of sx is
begin
process(en,data_reg,data_ram)is
begin
case en is
when '0'=>data_ram<=data_reg;
when'1'=>data_lcd<=data_ram;
when others=>data_ram<=(others=>'Z');
end case;
end process;
end art;