下面是一个8bit的进位加法器的测试模块,你看看时钟是怎么产生的
`timescale 1ns/1ns
module test;
reg rst;
reg clk;
reg [7:0]cina;
reg [7:0]cinb;
reg cin;
initial
begin
clk=0;
rst=0;
cin=0;
cina=8'b00000000;
cinb=8'b00000000;
#1150
rst=1;
#100000 $stop;
end
always #100 clk=~clk;
always @(posedge clk)
begin
cina={$random}%256;
cinb={$random}%256;
cin={$random}%2;
end
sum sum1(
.cina(cina),
.cinb(cinb),
.cin(cin),
.clk(clk),
.sum(sum),
.rst(rst),
.cout(cout)
);
endmodule |