有中文注释的完美8路ADC
library ieee;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_1164.all;
entity adc is
port(d :in std_logic_vector(7 downto 0);
clk,eoc :in std_logic; ---EOC:转换结束状态信号
oe : out std_logic; ---OE:输出允许,ADDA:选通地址
addrut std_logic_vector(2 downto 0);
ale,startut std_logic; ---ALE:允许地址锁存
qut std_logic_vector(7 downto 0); ---转换数据输出显示
qqut std_logic_vector(3 downto 0)
); ---即时状态输出显示
end adc;
architecture balu of adc is
type state is(st0,st1,st2,st3,st4,st5,st6,st7); ---以枚举类型状态定义各状态子类型
signal current_state,next_state:state:=st0;
signal regl :std_logic_vector(7 downto 0);
signal addrx :std_logic_vector(2 downto 0):="000";
signal lock :std_logic; ---转换后数据输出锁存时钟信号
begin
--addr<="011"; ---选通IN1通道
pro:process(current_state,eoc)
begin ---规定各状态转换方式,组合进程
case current_state is
when st0=> qq<="0000";ale<='0';start<='0';oe<='0';lock<='0';
next_state<=st1; ---初始态ST0向下一状态ST1转换,0809采样控制信号初始化
when st1=>qq<="0001";ale<='1';start<='0';oe<='0';lock<='0';
next_state<=st2; ---由ALE的上升沿将通道地址'001'锁入0809的地址寄存器
when st2=>qq<="0010";ale<='1';start<='1';oe<='0';lock<='0';
next_state<=st3; ---启动采样信号
when st3=>qq<="0011";ale<='0';start<='1';oe<='0';lock<='0';
if(eoc='0') then next_state<=st4; ---转换即将结束,转换至下一状态
else next_state<=st3; ---转换未结束,继续在状态ST3中等待
end if;
when st4=>qq<="0100";ale<='0';start<='0';oe<='0';lock<='0';
if(eoc='1') then next_state<=st5; ---EOC由0恢复1,转换结束
else next_state<=st4; ---转换未结束,等待
end if;
when st5=>qq<="0100";ale<='0';start<='0';oe<='1';lock<='0';
next_state<=st6; ---开启输出允许OE
when st6=>qq<="0101";ale<='0';start<='0';oe<='1';lock<='1';
next_state<=st7; ---关闭START,开启数据锁存LOCK
when st7=>qq<="0110";ale<='0';start<='0';oe<='0';lock<='1';
next_state<=st0; ---延时(一个脉冲)
when others=>next_state<=st0; ---其它状态返回ST0
end case;
end process;
process(clk) ---敏感信号CLK,作为时序进程
begin
if(clk'event and clk='1') then
current_state<=next_state; ---在时钟上升沿,转换至下一状态
end if;
end process ; ---由信号CURRENT_STATE将当前状态带出进程,进入PRO
process(lock) ---在CLOCK的上升沿,将转换好的数据锁存入8位锁存器中,得到稳定显示
begin
if lock='1'and lock'event then
regl<=d;
end if;
end process;
process(clk)
begin
if clk'event and clk='1'then
if current_state=st0 then
addrx<=addrx+1;
end if;
end if;
addr<=addrx;
end process;
q<=regl;
end balu; |