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求助用FPGA实现矩阵键盘的数码管显示,代码不知道哪里还有问题,就是不能正常显示键值,感觉显示都是乱码- module key4x4(kbrow,seg7_out,scan,clk,rst,kbcol);
- output[6:0] seg7_out;//7段显示控制信号(a,b,c,d,e,f,g)
- output[2:0] scan; //数码管段地址选择
- output[3:0] kbrow; //列扫描信号
- input rst; //复位信号
- input[3:0] kbcol; //行扫描信号
- input clk; //信号
- reg[6:0] seg7_out;
- reg[2:0] scan;
- reg[3:0] kbrow;
- reg[1:0] count;
- reg[1:0] sta;
- reg[6:0] seg7;
- reg[4:0] dat;
- reg fn; //按键按下 标志位 ,判断是否有按键按下
- initial scan<=3'b010; //只使用一个数码管显示
- always @(posedge clk)
- begin
- if(!rst)
- begin dat<=5'b10000;end//全灭
- else
- begin
- count<=count+1'b1; //循环扫描列 ,列扫描
- case(count)
- 2'b00: begin kbrow<=4'b1110;sta<=2'b00;end
- 2'b01: begin kbrow<=4'b1101;sta<=2'b01;end
- 2'b10: begin kbrow<=4'b1011;sta<=2'b10;end
- 2'b11: begin kbrow<=4'b0111;sta<=2'b11;end
- endcase //行扫描译
- case(sta)
- 2'b00:begin
- case(kbcol)
- 4'b1110:begin dat<=5'd3;end //3
- 4'b1101:begin dat<=5'd2;end //2
- 4'b1011:begin dat<=5'd1;end //1
- 4'b0111:begin dat<=5'd0;end //0
- default:begin dat<=5'b11111;end
- endcase
- end
- 2'b01:begin
- case(kbcol)
- 4'b1110:begin dat<=5'b00111;end //7
- 4'b1101:begin dat<=5'b00110;end //6
- 4'b1011:begin dat<=5'b00101;end //5
- 4'b0111:begin dat<=5'b00100;end //4
- default:begin dat<=5'b11111;end
- endcase
- end
- 2'b10:begin
- case(kbcol)
- 4'b1110:begin dat<=5'b01011;end //11 B
- 4'b1101:begin dat<=5'b01010;end //10A
- 4'b1011:begin dat<=5'b01001;end //9
- 4'b0111:begin dat<=5'b01000;end //8
- default:begin dat<=5'b11111;end
- endcase
- end
- 2'b11:begin
- case(kbcol)
- 4'b1110:begin dat<=5'b01111;end //15 F
- 4'b1101:begin dat<=5'b01110;end //14 E
- 4'b1011:begin dat<=5'b01101;end //13 D
- 4'b0111:begin dat<=5'b01100;end //12 C
- default:begin dat<=5'b11111;end
- endcase
- end
- endcase
- end
- end
- always @(dat)
- begin
- begin fn<=~(dat[0]&dat[1]&dat[2]&dat[3]&dat[4]);
- end
- case(dat)
- 5'b01111:begin seg7[6:0]<=7'b1110001;end
- 5'b01110:begin seg7[6:0]<=7'b1111001;end
- 5'b01101:begin seg7[6:0]<=7'b1011110;end
- 5'b01100:begin seg7[6:0]<=7'b0111001;end
- 5'b01011:begin seg7[6:0]<=7'b1111100;end
- 5'b01010:begin seg7[6:0]<=7'b1110111;end
- 5'd9:begin seg7[6:0]<=7'b1101111;end
- 5'd8:begin seg7[6:0]<=7'b1111111;end
- 5'd7:begin seg7[6:0]<=7'b0000111;end
- 5'd6:begin seg7[6:0]<=7'b1111101;end
- 5'd5:begin seg7[6:0]<=7'b1101101;end
- 5'd4:begin seg7[6:0]<=7'b1100110;end
- 5'd3:begin seg7[6:0]<=7'b1001111;end
- 5'd2:begin seg7[6:0]<=7'b1011011;end
- 5'd1:begin seg7[6:0]<=7'b0000110;end
- 5'd0:begin seg7[6:0]<=7'b0111111;end
- default: begin seg7[6:0]<=7'b0000000;end
-
- endcase
- end
- always @(posedge fn)
- begin seg7_out[6:0]<=seg7[6:0];
- end
- endmodule
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