频率计verilog源代码

频率计verilog源代码

这个例程是我自己做的一个简单的用原理图作为顶层文件，也是我给学生讲综合性实验的例子，希望能给初学者一些帮助！

密码？……

"#fre_counter.v"      顶层模块

module fre_counter(
                clk_50k,
                fre_in,
                rstn,
                led_sel,
                unit,
                a,b,c,d,e,f,g
                );
input clk_50k,fre_in,rstn;
output[1:0] led_sel;
output[2:0] unit;
output a,b,c,d,e,f,g;
//
//clk_genarator inst
wire div_10,div_100,div_1000,div_10000,div_100000;
clk_gen part_clk_gen(.rstn(rstn),.clk(clk_50k),.div_10(div_10),.div_100(div_100),.div_1000(div_1000),.div_10000(div_10000),.div_100000(div_100000));
//
//count inst
reg gate;
wire[3:0] count_a,count_b,count_c,count_d;
count_4units part_count(.clk(fre_in),.gate(gate),.out_a(count_a),.out_b(count_b),.out_c(count_c),.out_d(count_d));
//
reg[2:0] gate_sel;
assign unit=gate_sel;
wire unit_H;//?????????????????
reg unit_L;//???????????????????
always@(negedge count_a[3] or negedge gate)
  if(!gate) unit_L<=1'b0;
  else unit_L<=1'b1;
assign unit_H=((count_a==4'd0)&&(count_b==4'd0)&&(count_c==4'd0)&&(count_d==4'd0));
always@(negedge gate or negedge rstn)
begin
  if(!rstn) gate_sel<=3'd0;
  else if(unit_L&&(gate_sel!=3'd4)) gate_sel<=gate_sel+3'd1;
  else if(unit_H&&(gate_sel!=3'd0)) gate_sel<=gate_sel-3'd1;
  else gate_sel<=gate_sel;
end
always@(gate_sel or div_10 or div_100 or div_1000 or div_10000 or div_100000)
begin
  case(gate_sel)
    3'd0:gate=div_100000;
    3'd1:gate=div_10000;
    3'd2:gate=div_1000;
    3'd3:gate=div_100;
    3'd4:gate=div_10;
    default:gate=div_100000;
  endcase
end
//transform and led control
wire d_n0_a,d_n0_b,d_n0_c,d_n0_d;
wire a,b,c,d,e,f,g;
wire trans_ena_a,trans_ena_b,trans_ena_c,trans_ena_d;
wire ena_a,ena_b,ena_c,ena_d;
wire clk_lock;
assign clk_lock=~gate;
transform part_tran_a(.d_n0(d_n0_a),.din(count_a),.clk_lock(clk_lock),.ena(trans_ena_a),.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g));
transform part_tran_b(.d_n0(d_n0_b),.din(count_b),.clk_lock(clk_lock),.ena(trans_ena_b),.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g));
transform part_tran_c(.d_n0(d_n0_c),.din(count_c),.clk_lock(clk_lock),.ena(trans_ena_c),.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g));
transform part_tran_d(.d_n0(d_n0_d),.din(count_d),.clk_lock(clk_lock),.ena(trans_ena_d),.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g));

wire clk_ledc;
assign clk_ledc=div_1000;
led_sel part_led_sel(.rstn(rstn),.clk_ledc(clk_ledc),.led_ena({ena_a,ena_b,ena_c,ena_d}),.led_count(led_sel));

assign trans_ena_a=ena_a&d_n0_a;
assign trans_ena_b=ena_b&(d_n0_b|d_n0_a);
assign trans_ena_c=(d_n0_c|d_n0_b|d_n0_a)&ena_c;
assign trans_ena_d=ena_d;

endmodule


"#count_4units.v"      计数器模块（上层）
module count_4units(
              clk,
              gate,
              out_a,
              out_b,
              out_c,
              out_d
              );
input clk,gate;
output[3:0] out_a,out_b,out_c,out_d;
//
wire rst;
assign rst=~gate;

wire ena_c,ena_b,ena_a;


count c_d(.clk(clk),.ena(1'b1),.rst(rst),.qout(out_d),.full(ena_c));
count c_c(.clk(clk),.ena(ena_c),.rst(rst),.qout(out_c),.full(ena_b));
count c_b(.clk(clk),.ena(ena_b&ena_c),.rst(rst),.qout(out_b),.full(ena_a));
count c_a(.clk(clk),.ena(ena_a&ena_b&ena_c),.rst(rst),.qout(out_a),.full());

endmodule


"#count.v"                计数器模块（底层）
module count(
          clk,
          ena,
          rst,
          qout,
          full
          );
input clk,ena,rst;
output[3:0] qout;
output full;
//

//
reg[3:0] count;
always@(posedge rst or posedge clk)
begin
  if(rst)//a reset
    begin
      count<=4'b0000;
    end
  else if(ena)//one mux
    begin
      if(count==4'b1001) count<=4'b0000;//second mux
      else                count<=count+4'b0001;
    end
  else
    begin
      count<=count;
    end
end
//
assign qout=count;
assign full=(count==4'b1001);
endmodule







"#clk _gen.v"   分频模块（用于产生GATE信号）在GATE高电平时对输入信号计数
module clk_gen(
        clk,
        rstn,
        div_10,
        div_100,
        div_1000,
        div_10000,
        div_100000,
        );
input clk,rstn;
output div_10;
output div_100;
output div_1000;
output div_10000;
output div_100000;
//
//div_10
reg[2:0] count1;
always@(posedge clk or negedge rstn)
begin
  if(!rstn) count1<=3'd0;
  else if(count1==3'd4) count1<=3'd0;
  else             count1<=count1+3'd1;
end

reg  d1;
always@(posedge count1[2] or negedge rstn)
begin
  if(!rstn) d1<=1'd0;
  else d1<=~d1;
end
assign div_10=d1;
//
//div_100
reg[2:0] count2;
always@(posedge d1 or negedge rstn)
begin
  if(!rstn) count2<=3'd0;
  else if(count2==3'd4) count2<=3'd0;
  else             count2<=count2+3'd1;
end

reg  d2;
always@(posedge count2[2] or negedge rstn)
begin
  if(!rstn) d2<=1'd0;
  else d2<=~d2;
end

assign div_100=d2;
//
//div_1000
reg[2:0] count3;
always@(posedge d2 or negedge rstn)
begin
  if(!rstn) count3<=3'd0;
  else if(count3==3'd4) count3<=3'd0;
  else             count3<=count3+3'd1;
end

reg  d3;
always@(posedge count3[2] or negedge rstn)
begin
  if(!rstn) d3<=1'd0;
  else d3<=~d3;
end

assign div_1000=d3;
//
//div_10000
reg[2:0] count4;
always@(posedge d3 or negedge rstn)
begin
  if(!rstn) count4<=3'd0;
  else if(count4==3'd4) count4<=3'd0;
  else             count4<=count4+3'd1;
end

reg  d4;
always@(posedge count4[2] or negedge rstn)
begin
  if(!rstn) d4<=1'd0;
  else d4<=~d4;
end

assign div_10000=d4;
//
//div_100000
reg[2:0] count5;
always@(posedge d4 or negedge rstn)
begin
  if(!rstn) count5<=3'd0;
  else if(count5==3'd4) count5<=3'd0;
  else             count5<=count5+3'd1;
end

reg  d5;
always@(posedge count5[2] or negedge rstn)
begin
  if(!rstn) d5<=1'd0;
  else d5<=~d5;
end

assign div_100000=d5;
endmodule  

"#led_sel.v"      LED动态输出控制模块
module led_sel(
            rstn,
            clk_ledc,
            led_ena,
            led_count
            );
parameter LED_NUM=4;
parameter COUNT_BIT=2;
input clk_ledc,rstn;
output[LED_NUM:1] led_ena;
output[COUNT_BIT:1] led_count;
//
reg[COUNT_BIT:1] count;
assign led_count=count;
always@(posedge clk_ledc or negedge rstn)
begin
  if(!rstn) count<=2'd0;
  else count<=count+2'd1;
end
//
reg[LED_NUM:1] led_ena;
always@(count)
begin
  case(count)
    2'd0:led_ena=4'b0001;
    2'd1:led_ena=4'b0010;
    2'd2:led_ena=4'b0100;
    2'd3:led_ena=4'b1000;
    default:led_ena=4'b0000;
  endcase
end
endmodule




"#transform.v"                          十进制到LED译码模块
module transform(
                din,
                clk_lock,
                ena,
                d_n0,
                a,
                b,
                c,
                d,
                e,
                f,
                g
                );
input[3:0] din;
input ena,clk_lock;
output a,b,c,d,e,f,g;
output d_n0;
//
reg[3:0] locked_d;
always@(posedge clk_lock) locked_d<=din;
//
reg[6:0] codecache;
always@(locked_d)
begin
  case(locked_d)
    4'd0:codecache<=7'b1111110;
    4'd1:codecache<=7'b0110000;
    4'd2:codecache<=7'b1101101;
    4'd3:codecache<=7'b1111001;
    4'd4:codecache<=7'b0110011;
    4'd5:codecache<=7'b1011011;
    4'd6:codecache<=7'b1011111;
    4'd7:codecache<=7'b1110000;
    4'd8:codecache<=7'b1111111;
    4'd9:codecache<=7'b1111011;
    default:codecache<=7'bzzzzzzz;
  endcase
end
//
assign {a,b,c,d,e,f,g}=ena?codecache:7'bzzzzzzz;
assign d_n0=(locked_d!=4'd0);
endmodule

这么多！不知道用的什么型号板子调试！！

你好！我现在用Verilog也写了一个等精度频率计数器，并且用LDC1602十六进制显示，但是现在计数不准，计算的频率也有错。能麻烦你帮我改改吗？