额 高手帮下忙

要做个课设 基于FPGA的直接数字合成频率计
输出可调的正弦信号就行  有没有高手有的  发下邮箱466108954@qq.com  3Q
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
LIBRARY LPM;
USE LPM.LPM_COMPONENTS.ALL;
ENTITY ddsc IS
  GENERIC(FREQ_WIDTH:INTEGER:=32;
        PHASE_WIDTH:INTEGER:=12;
        ADDER_WIDTH:INTEGER:=32;
        ROMAD_WIDTH:INTEGER:=10;
        ROM_D_WIDTH:INTEGER:=10
       );
PORT(CLK:IN STD_LOGIC;
FREQIN:IN STD_LOGIC_VECTOR(FREQ_WIDTH-1 DOWNTO 0);
PHASEIN:IN STD_LOGIC_VECTOR(PHASE_WIDTH-1 DOWNTO0);
DDSOUT:OUT STD_LOGIC_VECTOR(ROM_D_WIDTH-1 DOWNTO0));
END ENTITY ddsc;
ARCHITECTURE BEHAVE OF ddsc IS
  SIGNAL ACC:STD_LOGIC_VECTOR(ADDER_WIDTH-1 DAOWNTO0);
  SIGNAL PHASEEADD:STD_LOGIC_VECTOR(PHASE_WIDTH-1 DAOWNTO0);
  SIGNAL ROMADDER:STD_LOGIC_VECTOR(ROMAD_WIDTH-1 DAOWNTO0);
  SIGNAL FREQW:STD_LOGIC_VECTOR(FREQ_WIDTH-1 DAOWNTO0);
SIGNAL PHASEW:STD_LOGIC_VECTOR(PHASE_WIDTH-1 DAOWNTO0);
BEGIN
PROCESS(CLK)
BEGIN
IF (CLK'EVENT AND CLK='1')THEN
FQERQ<=FREQIN;
PHASEW<=PHASEIN;
ACC<=ACC+FREQW;
END IF;
END PROCESS;
PHASEADD<=ACC(ADDER_WIDTH-1 DOWNTO ADDER_WIDTH-PHASE_WIDTH)+PHASEW;
ROMADDR<=PHASEADD(PHASE_WIDTH-1 DOWNTO PHASE_WIDTH-ROMAD_WIDTH);
--SIN-ROM
i_ROMPM_ROM
GENERIC MAP(LPM_WIDTH=>ROM_D_WIDTH,
        LPM_WIDTHAD=>ROM_WIDTH,
LPM_ADDRESS_CONTROL=>"UNREGISTERED",
LPM_OUTDATA=>"SIN_ROM.MIF")
PORT MAP(OUTCLOCK=>CLK,
ADDRESS=>ROMADDER,
Q=>DDSOUT);
END ACHITECTURE BEHAVE;