FPGA设计的电子时钟verilog语言(warning)

我用verilog语言设计的电子时钟程序，烧写到开发板中，分钟和秒钟的走时正常，可是小时的两个数码管始终没有显示，分钟计到59后，小时也不计1，始终显示00，请求那位高手帮我解决一下！这篇比较全，产生的所有warning都被我一一列出。万分感谢！
module clock_ver1(clr_key,clk,segdat,sl);
input clr_key;//复位信号，低电平有效
input clk;//系统时钟20MHZ
output[7:0]segdat;//八段数码管显示输出
output[5:0]sl;//数码管位选
reg[24:0]count;//对系统时钟进行计数
reg[7:0]sec,min,hou;//分、秒的八位寄存器
reg[7:0]segdat_reg;//数码管显示输出寄存器
reg[5:0]sl_reg;//数码管位选寄存器
reg[5:0]disp_dat;//数码管分、秒显示
reg second;//分频后产生1HZ的秒信号
reg cn;//秒向分的进位，高有效
reg cn_hou;//分向时进位信号
//对系统时钟进行分频，产生1HZ信号
always@(posedge clk)
   begin
     count<=count+1'b1;
     if(count==25'd99999)
      begin
                count<=25'h000000;
                second<=~second;
      end
   end
//***********************************************************************//
//利用计数器的第十二、十三位选中分、秒
always@(count[12:10])
   begin
        case(count[12:10])
        3'b000:disp_dat<=sec[3:0];
        3'b001:disp_dat<=sec[7:4];
        3'b010:disp_dat<=min[3:0];
        3'b011:disp_dat<=min[7:4];
        3'b100:disp_dat<=hou[3:0];
        3'b101:disp_dat<=hou[7:4];
        default: disp_dat <= 4'bx;
        endcase
   end
//************************************************************************//
//八段数码管显示输出
always@(disp_dat)
   begin
        case(disp_dat)
        4'h0:segdat_reg<=8'hc0;
        4'h1:segdat_reg<=8'hf9;
        4'h2:segdat_reg<=8'ha4;
        4'h3:segdat_reg<=8'hb0;
        4'h4:segdat_reg<=8'h99;
        4'h5:segdat_reg<=8'h92;
        4'h6:segdat_reg<=8'h82;
        4'h7:segdat_reg<=8'hf8;
        4'h8:segdat_reg<=8'h80;
        4'h9:segdat_reg<=8'h90;
        default: segdat_reg <= 8'hx;
        endcase
     /*if((count[12:11]==2'b10)&second)
     segdat_reg=segdat_reg&8'b01111111;*/
  end
//***************************************************************************//
//位选
always@(count[12:10])
  begin
        case(count[12:10])
        3'b000:sl_reg<=6'b111110;
        3'b001:sl_reg<=6'b111101;
        3'b010:sl_reg<=6'b111011;
        3'b011:sl_reg<=6'b110111;
        3'b100:sl_reg<=6'b101111;
        3'b101:sl_reg<=6'b011111;
        default:sl_reg<=6'bx;
        endcase
  end
//****************************************************************************//
//秒计时
always@(posedge second )
  begin
    if(!clr_key)//复位
      begin
                sec[7:0]<=8'h0;
                cn<=0;
      end
    else
        begin
                        cn<=0;
                        sec[3:0]<=sec[3:0]+1;
                        if(sec[3:0]==4'd9)//秒低位计到十
              begin
                                sec[3:0]<=4'd0;
                                sec[7:4]<=sec[7:4]+1;
                                if(sec[7:4]==4'd5 && sec[3:0]==4'd9)//秒高位计到六
                  begin
                                        sec[7:4]<=4'd0;
                                        cn<=1'd1;
                  end
              end
        end
    end
//*******************************************************************//
//秒向分产生进位信号cn
always@(posedge cn)
  begin
    if(!clr_key)
      begin
       min[7:0]<=8'h0;
      end
    else
      begin
                min[3:0]<=min[3:0]+1'b1;
                if(min[3:0]==4'd9)
          begin
                        min[3:0]<=4'd0;
                        min[7:4]<=min[7:4]+1'b1;
                        if(min[7:4]==4'd5 && min[3:0] == 4'd9)
              begin
               min[7:4]<=4'd0;
               cn_hou <= 1'd1;
              end
          end
      end
  end
//*****************************************************************
//分向时产生进位信号an
always@(posedge cn_hou)
   begin
     if(!clr_key)
       begin
        hou[7:0]<=0;
       end
    else
      begin
        hou[3:0]<=hou[3:0]+1'b1;
        if(hou[3:0]==4'd9)
          begin
            hou[3:0]<=4'd0;
            hou[7:4]<=hou[7:4]+1'b1;
          end
            if(hou[7:4]==4'd2 && hou[3:0]==4'd3)
              begin
               hou[7:0]<=8'h0;
              end
              else
               hou[3:0]<=hou[3:0]+1'b1;
       end
   end  

assign segdat=segdat_reg;
assign sl=sl_reg;
endmodule

Warning (10235): Verilog HDL Always Construct warning at clock_ver1.v(29): variable "sec" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at clock_ver1.v(30): variable "sec" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at clock_ver1.v(31): variable "min" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at clock_ver1.v(32): variable "min" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at clock_ver1.v(33): variable "hou" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at clock_ver1.v(34): variable "hou" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at clock_ver1.v(84): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock_ver1.v(88): truncated value with size 32 to match size of target (4)
Warning: Output pins are stuck at VCC or GND
        Warning (13410): Pin "segdat[7]" is stuck at VCC
Warning: Found 14 output pins without output pin load capacitance assignment
        Info: Pin "segdat[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "sl[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "sl[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "sl[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "sl[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "sl[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "sl[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
        Info: Pin segdat[7] has VCC driving its datain port
Warning: Found pins functioning as undefined clocks and/or memory enables
        Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
        Info: Detected ripple clock "second" as buffer
        Info: Detected ripple clock "cn" as buffer

1）cn_hou 信号一直是1，没有变化。分向时产生进位信号an 的模块被综合掉了。这是小时没有显示的原因
2）always@(count[12:10])
   begin
        case(count[12:10])
        3'b000:disp_dat<=sec[3:0];
        3'b001:disp_dat<=sec[7:4];
        3'b010:disp_dat<=min[3:0];
        3'b011:disp_dat<=min[7:4];
        3'b100:disp_dat<=hou[3:0];
        3'b101:disp_dat<=hou[7:4];
        default: disp_dat <= 4'bx;
        endcase
   end
这个模块中always敏感列表不全，建议改为always@(*)
3)second ,cn,cn_hou被当成时钟用了，这不是好的编码风格，应该尽量避免

我按照您的建议改了一下，警告还剩下5个，但小时的数码管始终还是显示00，分与秒钟正常，我试着将小时与秒钟的位选调了一下位置在第三个case语句那里，这时小时走的就正常了，可是显示的是秒：分：时，正好弄到了，我估计是扫描那里出了问题，麻烦您能再帮我看一下吗？
module clock_ver1(clr_key,clk,segdat,sl);
input clr_key;//复位信号，低电平有效
input clk;//系统时钟20MHZ
output[7:0]segdat;//八段数码管显示输出
output[5:0]sl;//数码管位选
//output spk;
//reg spk;//扬声器输出
reg[24:0]count;//对系统时钟进行计数
reg[7:0]sec,min,hou;//分、秒的八位寄存器
reg[7:0]segdat_reg;//数码管显示输出寄存器
reg[5:0]sl_reg;//数码管位选寄存器
reg[5:0]disp_dat;//数码管分、秒显示
reg second;//分频后产生1HZ的秒信号
reg cn;//秒向分的进位，高有效
reg cn_hou;//分向时进位信号
//reg[2:0]music_count;//产生扬声器声音频率的分频计数器
//对系统时钟进行分频，产生1HZ信号
always@(posedge clk)
   begin
     count<=count+1'b1;
     if(count==25'd99999)
      begin
                count<=25'h000000;
                second<=~second;
      end
   end
//***********************************************************************//
//利用计数器的第十二、十三位选中分、秒
always@(count[12:10] or sec or min or hou)
   begin
        case(count[12:10])
        3'b000:disp_dat<=sec[3:0];
        3'b001:disp_dat<=sec[7:4];
        3'b010:disp_dat<=min[3:0];
        3'b011:disp_dat<=min[7:4];
        3'b100:disp_dat<=hou[3:0];
        3'b101:disp_dat<=hou[7:4];
        default: disp_dat <= 4'bx;
        endcase
   end
//************************************************************************//
//八段数码管显示输出
always@(disp_dat)
   begin
        case(disp_dat)
        4'h0:segdat_reg<=8'hc0;
        4'h1:segdat_reg<=8'hf9;
        4'h2:segdat_reg<=8'ha4;
        4'h3:segdat_reg<=8'hb0;
        4'h4:segdat_reg<=8'h99;
        4'h5:segdat_reg<=8'h92;
        4'h6:segdat_reg<=8'h82;
        4'h7:segdat_reg<=8'hf8;
        4'h8:segdat_reg<=8'h80;
        4'h9:segdat_reg<=8'h90;
        default: segdat_reg <= 8'hx;
        endcase
     /*if((count[12:11]==2'b10)&second)
     segdat_reg=segdat_reg&8'b01111111;*/
  end
//***************************************************************************//
//位选
always@(count[12:10])
  begin
        case(count[12:10])
        3'b100:sl_reg<=6'b111110;
        3'b101:sl_reg<=6'b111101;
        3'b010:sl_reg<=6'b111011;
        3'b011:sl_reg<=6'b110111;
        3'b000:sl_reg<=6'b101111;
        3'b001:sl_reg<=6'b011111;
        default:sl_reg<=6'bx;
        endcase
  end
//****************************************************************************//
//秒计时
always@(posedge second or negedge clr_key)
  begin
    if(!clr_key)//复位
      begin
                sec[7:0]<=8'h0;
                cn<=0;
      end
    else
        begin
                        cn<=0;
                        sec[3:0]<=sec[3:0]+1'd1;
                        if(sec[3:0]==4'd9)//秒低位计到十
              begin
                                sec[3:0]<=4'd0;
                                sec[7:4]<=sec[7:4]+1'd1;
                                if(sec[7:4]==4'd5 && sec[3:0]==4'd9)//秒高位计到六
                  begin
                                        sec[7:4]<=4'd0;
                                        cn<=1'd1;
                  end
              end
        end
    end
//*******************************************************************//
//秒向分产生进位信号cn
always@(posedge cn or negedge clr_key)
  begin
    if(!clr_key)
      begin
       min[7:0]<=8'h0;
       cn_hou <=1'd 0;
      end
    else
      begin
       cn_hou <= 1'd0;
                min[3:0]<=min[3:0]+1'd1;
                if(min[3:0]==4'd9)
          begin
                        min[3:0]<=4'd0;
                        min[7:4]<=min[7:4]+1'd1;
                        if(min[7:4]==4'd5 && min[3:0] == 4'd9)
              begin
               min[7:4]<=4'd0;
               cn_hou <= 1'd1;
              end
          end
      end
  end
//*****************************************************************
//分向时产生进位信号cn_hou
always@(posedge cn_hou or negedge clr_key)
   begin
     if(!clr_key)
       begin
        hou[7:0]<=8'h0;
       end
    else
      begin
       // hou[3:0]<=hou[3:0]+4'd1;
         if(hou[3:0]==4'd9)
          begin
            hou[3:0]<=4'd0;
            hou[7:4]<=hou[7:4]+4'd1;
          end
          else  if(hou[7:4]==4'd2 && hou[3:0]==4'd3)
              begin
               hou[7:0]<=8'h0;
              end
          else
               hou[3:0]<=hou[3:0]+4'd1;
       end
   end  

assign segdat=segdat_reg;
assign sl=sl_reg;
endmodule
Warning: Output pins are stuck at VCC or GND
        Warning (13410): Pin "segdat[7]" is stuck at VCC
Warning: Found 14 output pins without output pin load capacitance assignment
        Info: Pin "segdat[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "segdat[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "sl[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "sl[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "sl[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "sl[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "sl[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
        Info: Pin "sl[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
        Info: Pin segdat[7] has VCC driving its datain port
Warning: Found pins functioning as undefined clocks and/or memory enables
        Info: Assuming node "clk" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
        Info: Detected ripple clock "second" as buffer
        Info: Detected ripple clock "cn" as buffer
        Info: Detected ripple clock "cn_hou" as buffer

FPGA设计的电子时钟verilog语言(warning)

FPGA设计的电子时钟verilog语言