2114| 1
|
想问一下,最近写verilog在QUARTUS中综合布局布线。发现点了compile之后 |
| ||
|小黑屋|手机版|Archiver|fpga论坛|fpga设计论坛
( 京ICP备20003123号-1 )
GMT+8, 2025-5-6 12:06 , Processed in 0.061612 second(s), 20 queries .
Powered by Discuz! X3.4
© 2001-2023 Discuz! Team.