AHDL to VHDL

用Xilinx的xport.exe 可以把ABLE和AHDL转换成VHDL或VerilogHDL

Solution

To convert AHDL to VHDL, use the Xport function from a command window as follows:

Usage: XPort [options] <input_top_module_files>

Options:
-abel process input file as an ABEL file
-ahdl process input file as an AHDL file
-list produce a listing of the input file(s); useful when more context is needed for messages
-vlg set output format to Verilog
-vhdl set output format to VHDL

If the -abel or the -ahdl option is not specified, AHDL input is assumed for files with a .tdf extension; otherwise, ABEL is assumed.

The default output format is Verilog.

Child module files are expected to be located in the same directory as the top module file name, which is specified on the command line.

AHDL conversion supports AHDL Version 8 with the following exceptions:

- Parameterized modules are converted with their invoked parameter values applied. Two-dimensional arrays are converted to one dimension.
- ABEL conversion is completed in a device-independent mode.
- Any implicit features implied by the ABEL device statement are ignored.
- ABEL test vectors are also converted and written to a separate test bench file, which has the prefix "tb_."
- ABEL Xilinx property statements are written to a separate constraint file, which has the file extension ".ncf."

Xport is provided to help migrate AHDL and ABEL designs to Verilog and VHDL and can process 90-95% of the designs without manual editing of the source or the result. Xport is provided "As-is." The ability to successfully convert an ABEL or AHDL design is not guaranteed, and converted designs should be functionally verified for use.

Xilinx AR#        17000