职位标签: FPGA
职位职能: 高级硬件工程师 硬件工程师
职位描述:
职位简介:
The FPGA design verification engineer will be the key participant in complex networking FPGA/ASIC development.
工作职责(Responsibilities):
The verification engineer will participate or own functional spec, write verification plan, build verification environment, write testcase, run simulation (include gate level) and debug the design, be responsible for design quality by achieving certain coverage goal.Required
职位需求(Requirement):
Experience with Vera or SystemVerilog is a must
Significant verification experience on complex ASICs/FPGAs verification
Knowledge of OOP programming
Experience on random, pseudo-random based verification
Experience on functional coverage
Basic logic design skill (verilog RTL coding, basic design structure) is necessary
Basic knowledge of networking concepts
Desired Skills:
In-depth knowledge of the advanced verification methodologies (such as RVM/VMM/UVM)
Programming using script language (such as unix shell, Perl, Tcl, etc)
Education:
Requires MSEE or BSEE/CS degree equivalent plus significant experience in design verification (3~5 years). |