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本帖最后由 fpgaw 于 2010-11-18 16:26 编辑
module cio_state (wr,rd,bit0,pointer_en,control_en);
input wr;
input rd;
input bit0;
output pointer_en;
output control_en;
reg pointer_en;
reg control_en;
reg [1:0] state;
parameter reset=2'b00,state0=2'b01,state1=2'b10;
always @ (bit0 or wr or rd)
if (bit0==1)
begin
state<=reset;
pointer_en<=1;
control_en<=0;
end
else
case (state)
reset:begin
if(wr==0 && bit0==0)
begin
state<=state0;
pointer_en<=0;
control_en<=1;
end
else begin
state<=reset;
pointer_en<=1;
control_en<=0;
end
end
state0:begin
if (wr==0)
begin
state<=state1;
pointer_en<=1;
control_en<=0;
end
else begin
state<=state0;
pointer_en<=0;
control_en<=1;
end
end
state1:begin
if (wr==0 && bit0==1)
begin
state<=reset;
pointer_en<=1;
control_en<=0;
end
else if (rd==0 || wr==0)
begin
state<=state0;
pointer_en<=0;
control_en<=1;
end
end
default:begin
state<=reset;
pointer_en<=1;
control_en<=0;
end
endcase
endmodule |
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