状态机的速度

在各个FPGA厂商的主流器件上，一个只有四个状态的状态机依次转换（不进行任何条件判断），能跑到多少频率啊？

你综合一下看看,综合工具会告诉你一个大概的

仅仅是综合是不够的还要映射到具体器件上面<br>
因为我自己的器件上好像有问题所以请大家帮我试试

附上程序：<br>
`timescale 1ns/1ps<br>
module fsm(sys_CLK, sys_RESET, iState);<br>
&nbsp;&nbsp;<br>
&nbsp; &nbsp;&nbsp; &nbsp; input&nbsp;&nbsp;sys_CLK, sys_RESET;<br>
&nbsp; &nbsp;&nbsp; &nbsp; output[1:0] iState;<br>
&nbsp; &nbsp;&nbsp; &nbsp; reg[1:0] iState;&nbsp;&nbsp;<br>
&nbsp; &nbsp;&nbsp; &nbsp; parameter&nbsp;&nbsp;state1&nbsp; &nbsp;&nbsp; &nbsp;= 2'b00,<br>
&nbsp; &nbsp;&nbsp; &nbsp; state2&nbsp; &nbsp;&nbsp; &nbsp;= 2'b01, <br>
&nbsp; &nbsp;&nbsp; &nbsp; state3&nbsp; &nbsp;&nbsp; &nbsp;= 2'b11,<br>
&nbsp; &nbsp;&nbsp; &nbsp; state4&nbsp; &nbsp;&nbsp; &nbsp;= 2'b10;<br>
always @(posedge sys_CLK)<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;begin <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;if (sys_RESET)&nbsp; &nbsp;&nbsp; &nbsp; iState &lt;= state1;<br>
&nbsp; &nbsp;else<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;case (iState)<br>
&nbsp;&nbsp;state1: <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;iState &lt;= state2;<br>
&nbsp;&nbsp;state2:<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;iState &lt;= state3;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;state3:<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;iState &lt;= state4;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;state4:<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; iState &lt;= state1;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;default:<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;iState &lt;= state1;<br>
&nbsp; &nbsp;&nbsp; &nbsp; endcase<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;end<br>
endmodule<br>
<br>
`timescale 1ns/1ps<br>
module test();<br>
&nbsp; &nbsp;&nbsp; &nbsp; reg&nbsp; &nbsp;sys_CLK, sys_RESET;<br>
&nbsp; &nbsp;&nbsp; &nbsp; wire[1:0]&nbsp;&nbsp;iState;<br>
&nbsp; &nbsp;&nbsp; &nbsp; initial<br>
&nbsp; &nbsp;begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; sys_CLK&nbsp; &nbsp;&nbsp; &nbsp; = 0;<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;sys_RESET&nbsp; &nbsp;&nbsp;&nbsp;= 1; <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;# 160 sys_RESET = 0;<br>
&nbsp; &nbsp;end<br>
&nbsp;&nbsp;always # 4 sys_CLK = ~sys_CLK;<br>
&nbsp;&nbsp;fsm&nbsp;&nbsp;M<br>
&nbsp; &nbsp;&nbsp; &nbsp; (.sys_CLK (sys_CLK),<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;.sys_RESET (sys_RESET), <br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;.iState (iState)<br>
&nbsp; &nbsp;&nbsp; &nbsp; );<br>
endmodule<br>
大家帮帮忙吧！

我再顶啊，没人理我

这种状态机的写法好像不太好吧<br>
组合逻辑和时序逻辑应该配合使用来实现状态机的变化<br>
我最高综合后可达90多Mhz<br>
实际上板还要看具体环境

ricewater : 为什么这样状态机的写法不太好. 能够说的仔细一些吗?

这里有一篇讲状态机的<br>
慢慢捉摸吧

Simple State machine don't need to use complicate style, I think his code is good enough for this simple one.

为什么不好呢?