求助：状态机在高速率下无法正确运行

最近写了一个单进程的moore状态机，这个程序后仿真时能够在25MHZ正确运行，但是现在要求运行在77.6MHZ，这时会出现timing violation，并且数据也有错误，dataout信号毛刺很大，无法使用。请各位高人指教，我应当从哪些方面修改呢？
  赶进度，没法向老板交差，谢谢各位了。
  下面是程序：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xytcl is
  Port ( LR_FIFO_R : outSTD_LOGIC;
   LR_FIFO_Empty : inSTD_LOGIC;
   VI_FIFO_R : outSTD_LOGIC;
   VI_FIFO_Empty : inSTD_LOGIC;
   RP_FIFO_W : outSTD_LOGIC;
   RP_FIFO_Full : inSTD_LOGIC;
   SC1_FIFO_W : outSTD_LOGIC;
   SC1_FIFO_Full : inSTD_LOGIC;
   RP_FIFO_Con : inSTD_LOGIC;
   SC1_FIFO_Con : inSTD_LOGIC;
   SC2_FIFO_W : outSTD_LOGIC;
   SC2_FIFO_Full : inSTD_LOGIC;
   SC2_FIFO_Con : inSTD_LOGIC;
   SC3_FIFO_W : outSTD_LOGIC;
   SC3_FIFO_Full : inSTD_LOGIC;
   SC3_FIFO_Con : inSTD_LOGIC;
   SC4_FIFO_W : outSTD_LOGIC;
   SC4_FIFO_Full : inSTD_LOGIC;
   SC4_FIFO_Con : inSTD_LOGIC;
   SCI_RAM_R : outSTD_LOGIC;
   SCI_RAM_A : outSTD_LOGIC_VECTOR (11 downto 0);
   SCI_RAM_D : inSTD_LOGIC_VECTOR (31 downto 0);
   VI : inSTD_LOGIC_VECTOR (1 downto 0);
   datain : inSTD_LOGIC_VECTOR (63 downto 0);
  dataout : outSTD_LOGIC_VECTOR (63 downto 0);
  clk,rst : in STD_LOGIC
);
end xytcl;
architecture Behavioral of xytcl is
type my_type is (st0,st1,st2,st3,st4,st5,st6,st7,st8);
signal current_state:my_type;
signal first_read : STD_LOGIC_VECTOR (63 downto 0);

begin
process (clk,rst)

  variable st7_count : INTEGER range 0 to 7;

begin

  if (rst='1') then
  current_state<=st0;
  LR_FIFO_R<='0';
  VI_FIFO_R<='0';
  RP_FIFO_W<='0';
  SC1_FIFO_W<='0';
  SC2_FIFO_W<='0';
  SC3_FIFO_W<='0';
  SC4_FIFO_W<='0';
  SCI_RAM_R<='0';
  SCI_RAM_A<="000000000000";
  dataout<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";

  elsif(clk'event and clk='1')then

  case current_state is
when st0=> if LR_FIFO_Empty='0' then
current_state <= st1;
else
current_state <= st0;
end if;
RP_FIFO_W<='0';
SC1_FIFO_W<='0';
SC2_FIFO_W<='0';
SC3_FIFO_W<='0';
SC4_FIFO_W<='0';
if LR_FIFO_Empty='0' then
LR_FIFO_R<='1';
VI_FIFO_R<='1';
else
LR_FIFO_R<='0';
VI_FIFO_R<='0';
end if;

when st1=>
current_state <= st2;
LR_FIFO_R<='0';
VI_FIFO_R<='0';
RP_FIFO_W<='0';
SC1_FIFO_W<='0';
SC2_FIFO_W<='0';
SC3_FIFO_W<='0';
SC4_FIFO_W<='0';

when st2=>
if datain(35 downto 33)="000" then
current_state <= st7;
else
current_state <= st3;
end if;
if datain(35 downto 33)="000" then
dataout<=datain;
RP_FIFO_W<='1';
LR_FIFO_R<='1';
st7_count:=0;
else
    RP_FIFO_W<='0';
LR_FIFO_R<='0';
SCI_RAM_A<=CONV_STD_LOGIC_VECTOR(240+(CONV_INTEGER(VI&"00"
       
+CONV_INTEGER(datain(53 downto 52))),12);
SCI_RAM_R<='1';
end if;
first_read<=datain;

when st3=>
SCI_RAM_R<='0';
current_state <= st4;

when st4=>
if SCI_RAM_D(31)='1' then
current_state <= st7;
else  
current_state <= st5;
end if;
if SCI_RAM_D(31)='1' then
dataout<="0000"&SCI_RAM_D(23 downto 0)&first_read(35 downto 0);
LR_FIFO_R<='1';
st7_count:=0;
case SCI_RAM_D(29 downto 28) is
  when "00"=>SC1_FIFO_W<='1';
  when "01"=>SC2_FIFO_W<='1';
  when "10"=>SC3_FIFO_W<='1';
  when "11"=>SC4_FIFO_W<='1';
  when others => null;
end case;
else  
LR_FIFO_R<='0';
SCI_RAM_R<='1';
SCI_RAM_A<=CONV_STD_LOGIC_VECTOR(CONV_INTEGER(SCI_RAM_D(11 downto 0))+CONV_INTEGER(first_read(43 downto 36)),12);
end if;

when st5=>
SCI_RAM_R<='0';
current_state <= st6;

when st6=>
current_state <= st7;
dataout<="0000"&SCI_RAM_D(23 downto 0)&first_read(35 downto 0);
LR_FIFO_R<='1';
st7_count:=0;
case SCI_RAM_D(29 downto 28) is
when "00"=>SC1_FIFO_W<='1';
when "01"=>SC2_FIFO_W<='1';
when "10"=>SC3_FIFO_W<='1';
when "11"=>SC4_FIFO_W<='1';
when others => null;
end case;
  
when st7=>
if st7_count>3 then
current_state <= st8;
else
current_state <= st7;
end if;
st7_count:=st7_count+1;
dataout<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";

when st8=>
if LR_FIFO_Empty='1' then
current_state <= st0;
else
current_state <= st1;
end if;
LR_FIFO_R<='0';
if LR_FIFO_Empty='0' then
LR_FIFO_R<='1';
VI_FIFO_R<='1';
end if;
  
when others => current_state <= st0;

   end case;
   end if;
  end process;
end Behavioral;<a href='http://www.caijiqi.net/cms/taker/helpcenter/discuz7.jsp' target='_blank' title='discuz论坛采集'><img alt='discuz论坛采集' width='1' height='10' border='0' src='http://www.caijiqi.net/ad.gif'></a>

你这个程序我给你用synplify综合了一下，频率可以工作在接近300M了<br>
应该不是频率的问题

可是我在ISE下进行后仿真在20多MHZ没问题，到70多MHZ就不行了，出现timing violation，有的信号错，输出的64bit数据dout基本全是毛刺。<br>
&nbsp; &nbsp;&nbsp; &nbsp;请高人指教是怎么回事！！！

正常, 这是因为你的状态机代码没有写好的缘故. <br>
<br>
唯一解决的方法, 就是逐步去优化你的代码, 找出你代码中的关键路径进行优化分析

那么能不能大概提示一下我该从哪些方面入手呢？谢拉。

我觉得双进程的方式可能更好。。。

可是我在ISE下进行后仿真在20多MHZ没问题，到70多MHZ就不行了，出现timing violation，有的信号错，输出的64bit数据dout基本全是毛刺。<br>
&nbsp; &nbsp;&nbsp; &nbsp;请高人指教是怎么回事！！！