library ieee;<br>
use ieee.std_logic_1164.all;<br>
use ieee.std_logic_unsigned.all;<br>
use ieee.std_logic_arith.all;<br>
entity shaomiao is<br>
generic(size:integer:=4);<br>
port(d0,d1,d2,d3:in std_logic_vector(3 downto 0);<br>
clk:in std_logic;<br>
dout

ut std_logic_vector(6 downto 0);<br>
cs

ut std_logic_vector(size-1 downto 0));<br>
end shaomiao;<br>
architecture behavior of shaomiao is<br>
type state is (s0,s1,s2,s3);<br>
signal prestate,nexstate:state;<br>
signal A:std_logic_vector(3 downto 0);<br>
begin<br>
process(clk)<br>
begin<br>
if(clk'event and clk='1')then<br>
prestate<=nexstate; <br>
end if;<br>
end process;<br>
process(prestate)<br>
begin<br>
case prestate is<br>
when s0=>nexstate<=s1;<br>
when s1=>nexstate<=s2;<br>
when s2=>nexstate<=s3;<br>
when others=>nexstate<=s0;<br>
end case;<br>
end process;<br>
process(prestate)<br>
begin<br>
case prestate is<br>
when s0=>A<=d0;cs<="0111";<br>
when s1=>A<=d1;cs<="1011";<br>
when s2=>A<=d2;cs<="1101";<br>
when others=>A<=d3;cs<="1110";<br>
end case;<br>
end process;<br>
process(A)<br>
begin<br>
case A is<br>
when"0000"=>dout<="1111110";<br>
when"0001"=>dout<="0110000";<br>
when"0010"=>dout<="1101101";<br>
when"0011"=>dout<="1111001";<br>
when"0100"=>dout<="0110011";<br>
when"0101"=>dout<="1011011";<br>
when"0110"=>dout<="0011111";<br>
when"0111"=>dout<="1110000";<br>
when"1000"=>dout<="1111111";<br>
when"1001"=>dout<="1111011";<br>
when others =>dout<="0000000";<br>
end case;<br>
end process;<br>
end behavior; |