Position description:
- Take charge of test-bench design;
- Participate on RTL design;
- Participate on CPLD/FPGA debug and test;
Skill requirement:
- Master student, major in communication or electric;
- Have design experience of CPLD or FPGA;
- Have design experience of VHDL or Verilog;
- Have design experience of ISE or Quartus;
- Have design experience of Modelsim;
联系方式
电子邮箱: apply_shanghai@celestica.com