verilog 实现音乐出错了，请教？

1module main(en,Fout,Fin,Reset);
2inputen,Fin,Reset;
3output Fout;
4 reg  Fout=0;
5
6always @(posedge Fin)
7if(en==1)
8 begin
9repeat (50)        
10
11F_Div m1 (Fout,Fin,Reset,956);//Undefined variable: F_Div
12repeat (50)
13F_Div m2 (Fout,Fin,Reset,852);
14repeat(50)
15 F_Div m3 (Fout,Fin,Reset,758);
16repeat(50)
17 F_Div m3 (Fout,Fin,Reset,758);
18repeat (50)
19F_Div m2 (Fout,Fin,Reset,852);
20repeat (50)
21 F_Div m1 (Fout,Fin,Reset,956);
22repeat (50)
23F_Div m1 (Fout,Fin,Reset,956);
24repeat (50)
25 F_Div m2 (Fout,Fin,Reset,852);
26repeat (50)
27 F_Div m3 (Fout,Fin,Reset,758);
28 repeat (50)
29 F_Div m2 (Fout,Fin,Reset,852);
30 repeat (50)
31F_Div m1 (Fout,Fin,Reset,956);
  
  $finish;
end
endmodule

module F_Div(Fout,Fin,Reset,fn);

input  Fin,Reset;
output   Fout;
//output[7:0]cnt;
reg    Fout=0;
input[6:0] fn;
reg[7:0] cnt;

always @(posedge Fin)
if (!Reset)
  begin
   cnt=0;
   Fout=0;
  end
else
  if (cnt<fn/2-1)   
  cnt=cnt+1;  
  else
  begin
  cnt=0;
  Fout=~Fout;
  end  
endmodule

ERROR: E:/EE C/CPLD/1216/freq.v(11): Undefined variable: F_Div
ERROR: E:/EE C/CPLD/1216/freq.v(11): near "m1": expecting: '=' <=
ERROR: E:/EE C/CPLD/1216/freq.v(12): near "repeat":syntax error
ERROR: E:/EE C/CPLD/1216/freq.v(13): near "852": expecting: ')' ','
ERROR: E:/EE C/CPLD/1216/freq.v(15): near "758": expecting: ')' ','
ERROR: E:/EE C/CPLD/1216/freq.v(17): near "758": expecting: ')' ','
ERROR: E:/EE C/CPLD/1216/freq.v(19): near "852": expecting: ')' ','
ERROR: E:/EE C/CPLD/1216/freq.v(21): near "956": expecting: ')' ','
ERROR: E:/EE C/CPLD/1216/freq.v(23): near "956": expecting: ')' ','
ERROR: E:/EE C/CPLD/1216/freq.v(25): near "852": expecting: ')' ','
ERROR: E:/EE C/CPLD/1216/freq.v(27): near "758": expecting: ')' ','
ERROR: E:/EE C/CPLD/1216/freq.v(29): near "852": expecting: ')' ','
ERROR: E:/EE C/CPLD/1216/freq.v(31): near "956": expecting: ')' ','
最郁闷的是第一个错误，怎么会没有定义呢？

将F_DIV模块放到主模块前试试

repeat语句好像不能综合的啊！

F_Div m1 (Fout,Fin,Reset,956);&nbsp;&nbsp;<br>
<br>
这样的语句是不能放在 always@ construct 中的

感谢大家，我把F_Div m1 (Fout,Fin,Reset,956);&nbsp;&nbsp;改成F_Div m1 (Fout,Fin,Reset,n);&nbsp;&nbsp;并放在always前面，大致如下<br>
module main(en,Fout,Fin,Reset);<br>
input&nbsp; &nbsp;&nbsp;&nbsp;en,Fin,Reset;<br>
output&nbsp; &nbsp; Fout;<br>
<br>
reg[8:0]&nbsp;&nbsp;i=0;&nbsp;&nbsp;<br>
reg[11:0] n;<br>
F_Div m (Fout,Fin,Reset,n);<br>
<br>
always @(posedge Fin)<br>
if(en==1) <br>
&nbsp;&nbsp;begin&nbsp; &nbsp; &nbsp; &nbsp; <br>
<br>
&nbsp;&nbsp;for(i=0;i&lt;50;i=i+1)<br>
&nbsp; &nbsp;n=956;&nbsp; &nbsp; &nbsp; &nbsp; .....................从这里进入F_Div后就无法跳出来执行for(i=0;i&lt;50;i=i+1)n=852;了<br>
&nbsp;&nbsp;for(i=0;i&lt;50;i=i+1)<br>
&nbsp; &nbsp;n=852;<br>
<br>
请问如何从一个module中跳出来？

http://www.fpga4fun.com/MusicBox.html

象repeat这样的语句是根本没法综合出来的。这个代码离真正的实现还很远，而且编程风格不是一般的烂（恕我直言）。建议楼主再好好看看VERILOG方面的基础资料。

可以用一个事件触发<br>
定义一个event<br>
当n=..时触发时间,跳出always

repeat语句好像不能综合的啊！