本帖最后由 fpgaw 于 2010-7-18 11:09 编辑
其源程序为
module count(dain,sel,S,Y,W);
input [7:0]dain;
input [2:0]sel;
input S;
output Y;
output W;
reg Y;
reg W;
always @ (dain or sel or S) begin
if (S==1)
begin Y=0;W=1; end
else
case (sel)
3'b000: begin
Y = dain[0];W = ~dain[0]; end
3'b001:begin
Y = dain[1];W = ~dain[1]; end
3'b010:begin
Y = dain[2];W = ~dain[2]; end
3'b011: begin
Y = dain[3];W = ~dain[3]; end
3'b100: begin
Y = dain[4];W =~dain[4]; end
3'b101: begin
Y = dain[5];W =~ dain[5]; end
3'b110: begin
Y = dain[6];W =~ dain[6]; end
3'b111: begin
Y = dain[7];W =~ dain[7]; end
default: Y = 8'hxx;
endcase
end
endmodule
测试程序为:
module count_tb;
reg[2:0]sel ;
reg[7:0]dain ;
wire Y ;
wire W ;
reg S ;
count
DUT(
.sel (sel ) ,
.dain (dain ) ,
.Y (Y ) ,
.W (W ) ,
.S (S ) );
initial
begin
S=1;
#2 sel=3'b000;dain=8'b00000001;
#2 sel=3'b001;dain=8'b00000010;
#2 sel=3'b010;dain=8'b00000100;
#2 sel=3'b011;dain=8'b00001000;
#2 sel=3'b100;dain=8'b00010000;
#2 sel=3'b101;dain=8'b00100000;
#2 sel=3'b110;dain=8'b01000000;
#2 sel=3'b111;dain=8'b10000000;
end
always begin
#2 S=0;
end
endmodule |