verilog 中的函数(tunction)如何用？

哪位大哥知道在verilog中怎么用函数function呀，我今天照着书上写了一个，可是不知道该怎么调用，谁写过完整的程序传上来一个吧

module test(con,...);<br>
input&nbsp;&nbsp;con;<br>
...<br>
//定义一个函数a<br>
function [3:0]&nbsp;&nbsp;a;<br>
input&nbsp; &nbsp;operate; <br>
begin<br>
&nbsp; &nbsp;&nbsp; &nbsp; if (operate)<br>
&nbsp; &nbsp;&nbsp; &nbsp; begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp;&nbsp;a&nbsp;&nbsp;= (2'b01)*(2'b11);<br>
&nbsp; &nbsp;&nbsp; &nbsp; end&nbsp;&nbsp;<br>
end<br>
endfunction<br>
<br>
reg [3:0] result;<br>
always @ ( * )<br>
begin<br>
&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp;&nbsp; &nbsp; result&nbsp;&nbsp;= a(con);&nbsp; &nbsp; //调用已经定义的一个函数a,con值传递给operate<br>
end<br>
<br>
endmodule

好象有点道理啊，谢谢

看过<br>
谢谢