RAM读写

ICE · 发表于 2010-6-27 23:34:39

----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
------------------------ ENTITY DECLARATION --------------------------------------
entity ram is
generic (ADDRES : INTEGER := 7;
DWIDTH : integer := 8;
DEPTH: integer :=128);

port (clk_i : instd_logic; -- clock signal
 reset_i : instd_logic; -- reset signal
 ram_data_i : instd_logic_vector(DWIDTH-1 downto 0);-- data input
 ram_data_o : out std_logic_vector(DWIDTH-1 downto 0);-- data output
 ram_adr_i: instd_logic_vector(ADDRES-1 downto 0);-- adresses
 ram_wr_i : instd_logic; -- read=0, write=1
 ram_en_i : instd_logic); -- inactive=0;active=1
end ram;
-----------------------------------------------------------------------------------
architecture sim of ram is
type ram_type is array (DEPTH-1 downto 0) of unsigned(DWIDTH-1 downto 0);
signals_gpram: ram_type; -- general purpose RAM

begin
------------------------------------------------------------------------------------
-- ram_read
------------------------------------------------------------------------------------

p_read : process (clk_i, reset_i)
begin
 if reset_i='1' then
 ram_data_o <= (others=>'0');
 else
 if Rising_Edge(clk_i) then
ram_data_o <= std_logic_vector(s_gpram(conv_integer(unsigned(ram_adr_i))));
 end if;
 end if;
end process p_read;
------------------------------------------------------------------------------------
-- ram_write
------------------------------------------------------------------------------------
p_write : process (clk_i, reset_i, ram_en_i)
begin
 if reset_i='1' then
 s_gpram <= (others => (others =>'0')); -- reset every bit
 else
 if Rising_Edge(clk_i) then
 if ((ram_en_i='1') and (ram_wr_i='1')) then
 s_gpram(conv_integer(unsigned(ram_adr_i))) <= unsigned(ram_data_i);
 end if;
 end if;
 end if;
end process p_write;

end sim;

 请教大侠，在读RAM时ram_data_o <= std_logic_vector(s_gpram(conv_integer(unsigned(ram_adr_i)))) 这个语句是怎么动作的，他是怎么把地址单元说存储的数据读出送到ram_data_o的
 s_gpram(conv_integer(unsigned(ram_adr_i))) <= unsigned(ram_data_i) 这条语句又是怎么动作的，？？？SOS

usb · 发表于 2010-6-28 00:51:17

不用这么复杂的吧？ 
使用 
if(oe = '0') then 
     data_o <= ram1(conv_integer(addr)); 
    else 
     ram1(conv_integer(addr)) <= data_i; 
    end if; 
就可以了

longtim · 发表于 2010-6-28 02:38:01

确实哈 
……………………

CHA · 发表于 2010-6-28 02:43:43

看懂了一点点

yihui · 发表于 2011-1-14 14:44:59

sram的verilog程序
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: sram_test
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module sram_test( rst ,
 clkin ,

 sram_ab ,
 sram_db ,
 sram_wr ,
 sram_rd ,
 sram_cs ,
 sram_be ,
 error,
 task_start , //Start Testing ---LED1
 task_finish,//TestingFinish---LED2
 flash_ce,
 flash_oe,
 flash_we

 );
input rst ;
input clkin ;

output [17:0] sram_ab ;
output [1:0] sram_be ;
inout[15:0] sram_db ;
output sram_wr ;
output sram_rd ;
output sram_cs ;
output error;
output task_start ;
output task_finish;
output flash_ce,flash_oe,flash_we;
//ports
wire rst ;
wire clkin ;

reg [17:0] sram_ab ;
wire [15:0] sram_db ;
reg sram_wr ;
reg sram_rd ;

reg task_start ;
reg task_finish;
wire flash_ce=1;
wire flash_oe=1;
wire flash_we=1;
reg clk_2;
wire clk;
reg[2:0] STATE,NEXT;
reg error ;
reg[15:0] sram_db_reg;
reg[15:0] count ;
//parameters
parameter IDLE = 3'D0,
 WRITE_1= 3'D1,
 WRITE_2= 3'D2,
 READ_1 = 3'D3,
 READ_2 = 3'D4;

assignsram_cs = 1'b0;
assignsram_be = 2'd0;
assignsram_db = sram_rd ? sram_db_reg:'hz;

reg [1:0] clk_count;
always @(posedge clkin or negedge rst)
if(!rst)
begin
clk_count<=2'd0;
end
else
begin
 clk_count<=clk_count+1'b1;
end
assign clk = clk_count[1];

//state machine
always @ (STATE or sram_ab or error or task_start)
begin
case(STATE)
IDLE : if(task_start)
 NEXT = WRITE_1;
 else
 NEXT = IDLE ;
WRITE_1 : NEXT = WRITE_2;
WRITE_2 : if( sram_ab >= 18'h3ffff)
 NEXT = READ_1;
 else
 NEXT = WRITE_1;
READ_1: NEXT = READ_2;
READ_2: if(sram_ab >= 18'h3ffff)//error ||
 NEXT = IDLE;
 else
 NEXT = READ_1;
default : NEXT = IDLE ;
endcase
end

//registe the state
always @ (posedge clk or negedge rst)
if(!rst)
 STATE <= IDLE;
else
 STATE <= NEXT;

always @ (posedge clk or negedge rst)
if(!rst)
 begin
 sram_ab <=18'h3ffff;
 sram_db_reg<=16'h1fff;
 sram_wr <=1'b1;
 sram_rd <=1'b1;
 end
else
 case(STATE)
 IDLE : begin
 sram_rd <= 1;
 sram_wr <= 1;
end
 WRITE_1 : begin
 sram_ab <= sram_ab+1;
 sram_db_reg <= sram_db_reg+1;
 sram_wr <= 1'b0;
 sram_rd <= 1'b1;
end
 WRITE_2 : begin
 sram_wr<= 1'b1;
 sram_rd<= 1'b1;
end
 READ_1: begin
 sram_ab <= sram_ab+1;
 sram_wr <= 1'b1;
 sram_rd <= 1'b0;
 sram_db_reg <= 'h1fff;
end
 endcase

always @ (posedge clk or negedge rst)
if(!rst)
begin
error <= 1'b0;
task_start <= 1'b1;
task_finish<= 1'b0;
count <= 16'h1fff;
end
else
case(STATE)

WRITE_1 : //if( sram_ab < 'd1024 )
 begin
 task_start <= 1'b1;
 count <= 16'h1fff;
 end
READ_1: begin
 count<=count+1;
 end
READ_2: begin
 if( sram_db != count)
 error <= 1'b1;
 else
 begin
 error <= 1'b0;
 if(sram_ab >= 18'h3ffff)
 begin
 task_finish <= 1'b1;
 //task_start<= 1'b1;
 end
 end
 end
endcase

endmodule

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RAM读写

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