请verilog高手帮忙看看

module ram_c_count256(clk,rst,en,count256);
input clk;
input rst;
input en;
output [7:0]count256;
reg [7:0]count256;

always@(posedge clk or negedge rst or posedge en)
begin
if(!en)
  count256<=8'd0;
else if(rst)
  count256<=8'd0;
else if(count256==8'd255)
  count256<=8'd0;
else
  count256<=count256+8'd1;
end

endmodule
编译时提醒有序错误
Error: Verilog HDL Conditional Statement error at ram_c_count256.v(10): cannot match all operands in the condition expression to corresponding edges in the enclosing Always Construct's Event Control
Error: Verilog HDL Conditional Statement error at ram_c_count256.v(13): cannot match all operands in the condition expression to corresponding edges in the enclosing Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at ram_c_count256.v(16): variable "count256" is read inside the Always Construct but isn't in the Always Construct's Event Control
Error: Verilog HDL Conditional Statement error at ram_c_count256.v(16): cannot match all operands in the condition expression to corresponding edges in the enclosing Always Construct's Event Control
Warning: Verilog HDL Always Construct warning at ram_c_count256.v(19): variable "count256" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning: Verilog HDL warning at ram_c_count256.v(19): can't infer register for Procedural Assignment in Always Construct because the clock signal isn't obvious. Generated combinational logic instead.
Error: Can't elaborate user hierarchy ""
Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 3 warnings
    Error: Processing ended: Wed May 09 16:55:38 2007
    Error: Elapsed time: 00:00:06
请问该怎么改?
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 3 warnings

低电平异步复位和高电平异步使能的表达有问题<br>
列表中negedge rst所对应的if条件是!rst，不是rst<br>
列表中posedge en所对应的if条件使en，不是!en

longtim 发表于 2010-6-28 01:05
低电平异步复位和高电平异步使能的表达有问题
列表中negedge rst所对应的if条件是!rst，不是rst
列表中pose ...

太好了！解决了一个大问题！